參數(shù)資料
型號(hào)： SSTU32865EG
廠商： NXP Semiconductors N.V.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Linear Voltage Regulator IC; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No
中文描述： 1.8伏28位1:2登記緩沖區(qū)的DDR2 RDIMM特別平價(jià)
文件頁(yè)數(shù)： 10/29頁(yè)
文件大?。?/td> 157K
代理商： SSTU32865EG
9397 750 13799
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 28 September 2004
10 of 29
Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
7.3 Functional differences to SSTU32864
The SSTU32865 for its basic register functionality, signal definition and performance is
based upon the industry-standard SSTU32864, but provides key operational features
which differ (at least in part) from the industry-standard register in the following aspects:
7.3.1
Chip Select (CS) gating of key inputs (DCS0, DCS1, CSGATEEN)
As a means to reduce device power, the internal latches will only be updated when one or
both of the CS inputs are active (LOW) and CSGATEEN HIGH at the rising edge of the
clock. The 22 ‘Chip-Select-gated’ input signals associated with this function include
addresses (ADDR0 to ADDR15, BA0 to BA2), and RAS, CAS, WE, with the remaining
signals (CS, CKE, ODT) continuously re-driven at the rising edge of every clock as they
are independent of CS. The CS gating function can be disabled by tying CSGATEEN
LOW, enabling all internal latches to be updated on every rising edge of the clock.
7.3.2
Parity error checking and reporting
The SSTU32865 incorporates a parity function, whereby the signal received on input pin
PARIN is received as parity to the register, one clock cycle later than the CS-gated inputs.
The received parity bit is then compared to the parity calculated across these same inputs
by the register parity logic to verify that the information has not been corrupted. The 22
CS-gated input signals will be latched and re-driven on the first clock, and any error will be
reported one clock cycle later via the PTYERR output pin (driven LOW for two consecutive
clock cycles). PTYERR is an open-drain output, allowing multiple modules to share a
common signal pin for reporting the occurrence of a parity error during a valid command
cycle (coincident with the re-driven signals). This output is driven LOW for two consecutive
clock cycles to allow the memory controller sufficient time to sense and capture the error
even. A LOW state on PTYERR indicates that a parity error has occurred.
7.3.3
Reset (RESET)
Similar to the RESET pin on the industry-standard SSTU32864, this pin is used to clear all
internal latches and all outputs will be driven LOW quickly except the PTYERR output,
which will be floated (and will normally default HIGH by their external pull-up).
7.3.4
Power-up sequence
The reset function for the SSTU32865 is similar to that of the SSTU32864 except that the
PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive clock
cycles.
Table 5:
Mode
Gating
Chip Select gating mode
Signal name
CSGATEEN
HIGH
CSGATEEN
LOW
Description
Registers only re-drive signals to the DRAMs when
Chip Select inputs are LOW.
Non-gating
Registers always re-drive signals on every clock cycle,
independent of the state of the Chip Select inputs.
相關(guān)PDF資料
PDF描述
SSTUA32864 Linear Voltage Regulator IC; Package/Case:8-MSOP; Current Rating:250mA; Leaded Process Compatible:No; Output Voltage Max:1.8V; Peak Reflow Compatible (260 C):No; Reel Quantity:2500; Voltage Regulator Type:Low Dropout (LDO)
SSTUA32864EC Linear Voltage Regulator IC; Package/Case:8-MSOP; Current Rating:250mA; Leaded Process Compatible:No; Output Voltage Max:2.5V; Peak Reflow Compatible (260 C):No; Reel Quantity:2500; Voltage Regulator Type:Low Dropout (LDO)
SSTUA32864EG Linear Voltage Regulator IC; Package/Case:8-MSOP; Current Rating:250mA; Leaded Process Compatible:No; Output Voltage Max:2.8V; Peak Reflow Compatible (260 C):No; Reel Quantity:2500; Voltage Regulator Type:Low Dropout (LDO)
SSTVN16859 13-bit 1:2 SSTL_2 registered buffer for DDR
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTU32865ET 功能描述:寄存器 1.8V 28-BIT REG BUF/PARITY RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,518 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,551 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET,557 功能描述:寄存器 1.8V 28-BIT REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTU32865ET/G 功能描述:寄存器 1.8V 28-BIT REG BUF/PARITY RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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