
54
Preliminary Specifications
FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
2004 Silicon Storage Technology, Inc.
S71255-00-000
3/04
TABLE
8-5: PCA M
ODULE
M
ODES
Without Interrupt enabled
-
1
ECOMy
2
-
0
-
0
-
0
-
0
CAPPy
2
0
1
0
1
CAPNy
2
0
0
1
1
MATy
2
0
0
0
0
TOGy
2
0
0
0
0
PWMy
2
0
0
0
0
ECCFy
2
0
0
0
0
Module Code
No Operation
16-bit capture on positive-edge trigger at CEX[4:0]
16-bit capture on negative-edge trigger at CEX[4:0]
16-bit capture on positive/negative-edge
trigger at CEX[4:0]
Compare: software timer
Compare: high-speed output
Compare: 8-bit PWM
Compare: PCA WDT (CCAPM4 only)
4
-
-
-
-
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0 or 1
3
T8-5.0 1255
1. User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.
2. y = 0, 1, 2, 3, 4
3. A 0 disables toggle function. A 1 enables toggle function on CEX[4:0] pin.
4. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal.
TABLE
8-6: PCA M
ODULE
M
ODES
With Interrupt enabled
-
1
ECOMy
2
-
0
-
0
-
0
1. User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.
2. y = 0, 1, 2, 3, 4
3. No PCA interrupt is needed to generate the PWM.
4. A 0 disables toggle function. A 1 enables toggle function on CEX[4:0] pin.
5. Enabling an interrupt for the Watchdog Timer would defeat the purpose of the Watchdog Timer.
6. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal.
CAPPy
2
1
0
1
CAPNy
2
0
1
1
MATy
2
0
0
0
TOGy
2
0
0
0
PWMy
2
0
0
0
ECCFy
2
1
1
1
Module Code
16-bit capture on positive-edge trigger at CEX[4:0]
16-bit capture on negative-edge trigger at CEX[4:0]
16-bit capture on positive/negative-edge
trigger at CEX[4:0]
Compare: software timer
Compare: high-speed output
Compare: 8-bit PWM
Compare: PCA WDT (CCAPM4 only)
6
-
-
-
-
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
X
3
X
5
0 or 1
4
T8-6.0 1255