參數(shù)資料
型號: SST89V516RD2-40-I-NI
廠商: Silicon Storage Technology, Inc.
英文描述: FlashFlex51 MCU
中文描述: FlashFlex51單片機
文件頁數(shù): 35/91頁
文件大?。?/td> 984K
代理商: SST89V516RD2-40-I-NI
Preliminary Specifications
FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
35
2004 Silicon Storage Technology, Inc.
S71255-00-000
3/04
4.0 FLASH MEMORY PROGRAMMING
The device internal flash memory can be programmed or
erased using the following two methods:
External Host Programming mode
In-Application Programming (IAP) mode
4.1 External Host Programming Mode
External host programming mode allows the user to pro-
gram the flash memory directly without using the CPU.
External host mode is entered by forcing PSEN# from a
logic high to a logic low while RST input is being held con-
tinuously high. The device will stay in external host mode
as long as RST = 1 and PSEN# = 0.
A Read-ID operation is necessary to “arm” the device in
external host mode, and no other external host mode com-
mands can be enabled until a Read-ID is performed. In
external host mode, the internal flash memory blocks are
accessed through the re-assigned I/O port pins (see Figure
4-1 for details) by an external host, such as a MCU program-
mer, a PCB tester or a PC-controlled development board.
Note:
V
IL
= Input Low Voltage;
V
IH
= Input High Voltage;
V
IH1
= Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;
AH = Address high order byte; DI = Data Input; DO = Data Output; A[15:13] = 0xxb for Block 0 and A[15:13] = 111b for Block 1
TABLE
4-1: E
XTERNAL
H
OST
M
ODE
C
OMMANDS
FOR
SST89E/V5
X
RD2
Operation
Read-ID
Chip-Erase
Block-Erase
Sector-Erase
Byte-Program
Byte-Verify (Read)
Prog-SC0
Prog-SC1
Prog-SB1
Prog-SB2
Prog-SB3
Enable-Clock-Double
RST
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
PSEN#
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
PROG#/
ALE
V
IH
1
V
IH
EA#
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
P3[7]
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IH
P3[6]
V
IL
V
IL
V
IH
V
IL
V
IH
V
IH
V
IL
V
IL
V
IH
V
IL
V
IH
V
IL
P2[7]
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
P2[6]
V
IL
V
IH
V
IH
V
IH
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
P0[7:0]
DO
X
X
X
DI
DO
X
X
X
X
X
X
P3[5:4]
P2[5:0]
AH
X
A[15:13]
AH
AH
AH
5AH
AAH
X
X
X
55H
P1[7:0]
AL
X
X
AL
AL
AL
X
X
X
X
X
X
1. Symbol
signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input.
All other combinations of the above input pins are invalid and may result in unexpected behaviors.
T4-1.0 1255
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