- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365740 > SST89E564RD-40-C-NI (Silicon Storage Technology, Inc.) FlashFlex51 MCU PDF資料下載
參數(shù)資料
| 型號： | SST89E564RD-40-C-NI |
| 廠商： | Silicon Storage Technology, Inc. |
| 英文描述： | FlashFlex51 MCU |
| 中文描述： | FlashFlex51單片機 |
| 文件頁數(shù)： | 30/62頁 |
| 文件大小： | 680K |
| 代理商： | SST89E564RD-40-C-NI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
30
Preliminary Specifications
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
2001 Silicon Storage Technology, Inc.
S71207-00-000
9/01
555
The Byte-Verify command allows the user to verify that the
device correctly performed an Erase or Program com-
mand. This command will be disabled if any security locks
are enabled. See Figure 4-11 for timing waveforms.
The Prog-SB1, Prog-SB2, Prog-SB3 commands program
the security bits, the functions of these bits are described in
the Security Lock section and also in Table 9-1. Once pro-
grammed, these bits can only be erased through a Chip-
Erase command. See Figure 4-9 for timing waveforms.
Prog-SC0 command programs SC0 bit, which determines
the state of SFCF[0] out of reset. Once programmed, SC0
can only be restored to an erased state via a Chip-Erase
command. See Figure 4-10 for timing waveforms.
Prog-SC1 command programs SC1 bit, which determines
the state of SFCF[1] out of reset. Once programmed, SC1
can only be restored to an erased state via a Chip-Erase
command. See Figure 4-10 for timing waveforms. Prog-
SC1 is for SST89E554RC/SST89V554RC only.
4.1.4 External Host Mode Clock Source
In External Host Mode, an internal oscillator will provide
clocking for the device. The on-chip oscillator will be turned
on as the device enters External Host Mode; i.e. when
PSEN# goes low while RST is high. During External Host
Mode, the CPU core is held in reset. Upon exit from Exter-
nal Host Mode, the internal oscillator is turned off.
4.1.5 Flash Operation Status Detection Via External
Host Handshake
The device provides two methods for an external host to
detect the completion of a flash memory operation to opti-
mize the Program or Erase time. The end of a flash mem-
ory operation cycle can be detected by:
1. monitoring the Ready/Busy# bit at P3[3];
2. monitoring the Data# Polling bit at P0[3].
4.1.5.1 Ready/Busy# (P3[3])
The progress of the flash memory programming can be
monitored by the Ready/Busy# output signal. P3[3] is
driven low, some time after ALE/PROG# goes low during a
flash memory operation to indicate the Busy# status of the
Flash Control Unit (FCU). P3[3] is driven high when the
Flash programming operation is completed to indicate the
Ready status.
4.1.5.2 Data# Polling (P0[3])
During a Program operation, any attempts to read (Byte-
Verify), while the device is busy, will receive the comple-
ment of the data of the last byte loaded (logic low, i.e. “0” for
an erase) on P0[3] with the rest of the bits “0”. During a Pro-
gram operation, the Byte-Verify command is reading the
data of the last byte loaded, not the data at the address
specified.
4.1.6 Step-by-step instructions to perform
External Host Mode commands
To program data into the memory array, apply power
supply voltage (V
DD
) to V
DD
and RST pins, and per-
form the following steps:
1. Maintain RST high and set PSEN# from logic high
to low, in sequence according to the appropriate
timing diagram.
2. Raise EA# High (V
IH
).
3. Issue Read-ID command to enable the External
Host Mode.
4. Verify that the memory blocks or sectors for pro-
gramming is in the erased state, FFH. If they are
not erased, then erase them using the appropriate
Erase command.
5. Select the memory location using the address
lines (P3[5:4], P2[5:0], P1[7:0]).
6. Present the data in on P0[7:0].
7. Pulse ALE/PROG#, observing minimum pulse
width.
8. Wait for low to high transition on READY/BUSY#
(P3[3]).
9. Repeat steps 5 - 8 until programming is finished.
10. Verify the flash memory contents.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SST89V564RD-40-C-NI | FlashFlex51 MCU |
| SST89E564RD-40-C-NJ | FlashFlex51 MCU |
| SST89V564RD-40-C-NJ | FlashFlex51 MCU |
| SST89E564RD-40-C-PI | MCF547X V4ECORE MMU, FPU |
| SSTDPAD100 | Dual Low-Leakage Pico-Amp Diode(最大反向電流-100pA的雙低泄漏電流二極管) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST89E564RD-40-C-NJ | 功能描述:8位微控制器 -MCU 64KB+8KB 40ns RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| SST89E564RD-40-C-NJE | 功能描述:8位微控制器 -MCU 64KB+8KB 40ns RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| SST89E564RD-40-C-PI | 功能描述:8位微控制器 -MCU 64KB+8KB 40ns RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| SST89E564RD-40-C-PIE | 功能描述:8位微控制器 -MCU 64KB+8KB 40ns RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| SST89E564RD-40-C-PJ | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。