參數(shù)資料
型號： SST89E52RC-33-C-PIE
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PDIP40
封裝： ROHS COMPLIANT, PLASTIC, MS-011AC, DIP-40
文件頁數(shù)： 39/57頁
文件大?。?/td> 652K
代理商： SST89E52RC-33-C-PIE
44
Data Sheet
FlashFlex MCU
SST89E52RC / SST89E54RC
2007 Silicon Storage Technology, Inc.
S71259-04-000
1/07
11.0 SYSTEM CLOCK AND CLOCK OPTIONS
11.1 Clock Input Options and Recom-
mended Capacitor Values for Oscillator
Shown in Figure 11-1 are the input and output of an inter-
nal inverting amplifier (XTAL1, XTAL2), which can be con-
figured for use as an on-chip oscillator.
When driving the device from an external clock source,
XTAL2 should be left disconnected and XTAL1 should be
driven.
At start-up, the external oscillator may encounter a higher
capacitive load at XTAL1 due to interaction between the
amplifier and its feedback capacitance. However, the
capacitance will not exceed 15 pF once the external signal
meets the VIL and VIH specifications.
Crystal manufacturer, supply voltage, and other factors
may cause circuit performance to differ from one applica-
tion to another. C1 and C2 should be adjusted appropri-
ately for each design. Table 11-1, shows the typical values
for C1 and C2 vs. crystal type for various frequencies
More specific information about on-chip oscillator design
can be found in the FlashFlex Oscillator Circuit Design
Considerations application note.
11.2 Clock Doubling Option
By default, the device runs at 12 clocks per machine cycle
(x1 mode). The device has a clock doubling option to
speed up to 6 clocks per machine cycle. Please refer to
Table 11-2 for detail.
Clock double mode can be enabled either via the external
host mode or the IAP mode. Please refer to Table 4-3 for
the IAP mode enabling command (When set, the Enable-
Clock-Double_i bit in the SFST register will indicate 6-clock
mode.).
The clock double mode is only for doubling the inter-
nal system clock and the internal flash memory, i.e.
EA#=1. To access the external memory and the peripheral
devices, careful consideration must be taken. Also note
that the crystal output (XTAL2) will not be doubled.
11.3 Clock Divider Option
The device has an option to run at scaled-down clock rates
of 1/4, 1/16, 1/256, and 1/1024. The COEN bit in the
COSR register must be set to enable this option. The
CO_SEL bits are set to select the clock rate. See the
COSR register for more information.
FIGURE
11-1: Oscillator Characteristics
TABLE
11-1:Recommended Values for C1 and C2
by Crystal Type
Crystal
C1 = C2
Quartz
20-30pF
Ceramic
40-50pF
T11-1.1 1259
TABLE
11-2: Clock Doubling Features
Device
Standard Mode (x1)
Clock Double Mode (x2)
Clocks per
Machine Cycle
Max. External Clock Frequency
(MHz)
Clocks per
Machine Cycle
Max. External Clock Frequency
(MHz)
SST89E5xRC
12
33
6
16
T11-2.0 1259
1259 F28.0
XTAL2
XTAL1
VSS
C1
Using the On-Chip Oscillator
External Clock Drive
C2
XTAL2
XTAL1
VSS
External
Oscillator
Signal
NC
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