參數(shù)資料
型號(hào)： SST89C58-33-I-TQJE
廠商： SILICON STORAGE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44
封裝： LEAD FREE, TQFP-44
文件頁(yè)數(shù)： 51/52頁(yè)
文件大?。?/td> 967K
代理商： SST89C58-33-I-TQJE
8
Data Sheet
FlashFlex51 MCU
SST89C54 / SST89C58
2004 Silicon Storage Technology, Inc.
S71131-04-000
6/04
2.1 Pin Descriptions
TABLE
2-1: PIN DESCRIPTIONS (1 OF 2)
Symbol
Type1
Name and Functions
P0[7:0]
I/O
Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can
sink several LS TTL inputs. Port 0 pins that have ‘1’s written to them float, and in that state
can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and
data bus during accesses to external code and data memory. In this application it uses strong
internal pull-ups when transitioning to ‘1’s. Port 0 also receives the code bytes during the
external host mode programming, and outputs the code bytes during external host mode ver-
ification. External pull-ups are required during program verification or as a general purpose I/
O port.
P1[7:0]
I/O with internal
pull-ups
Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 output buffers can
drive LS TTL inputs. Port 1 pins that have ‘1’s written to them are pulled high by the internal
pull-ups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally
pulled low will source current (IIL, see Tables 12-6 and 12-7) because of the internal pull-ups.
P1[5, 6, 7] have high current drive of 16mA. Port 1 also receives the low-order address bytes
during external host mode programming and verification.
P1[0]
I
T2: External count input to Timer/Counter 2
P1[1]
I
T2EX: Timer/Counter 2 capture/reload trigger
P2[7:0]
I/O with internal
pull-ups
Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have ‘1’s
written to them are pulled high by the internal pull-ups, and in that state can be used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current (IIL, see Tables
12-6 and 12-7) because of the internal pull-ups. Port 2 sends the high-order address byte
during fetches from external Program memory and during accesses to external Data Memory
that use 16-bit address (MOVX@DPTR). In this application it uses strong internal pull-ups
when outputting ‘1’s. Port 2 also receives some control signals and a partial of high-order
address bits during the external host mode programming and verification.
P3[7:0]
I/O with internal
pull-ups
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers
can drive LS TTL inputs. Port 3 pins that have ‘1’s written to them are pulled high by the inter-
nal pull-ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current (IIL, see Tables 12-6 and 12-7) because of the internal pull-ups.
Port 3 serves the functions of various special features of the device. Port 3 also receives
some control signals and a partial of high-order address bits during the external host mode
programming and verification.
P3[0]
I
RXD: UART - Receive input
P3[1]
O
TXD: UART - Transmit output
P3[2]
I
INT0#: External Interrupt 0 input
P3[3]
I
INT1#: External Interrupt 1 input
P3[4]
I
T0: External Count input to Timer/Counter 0
P3[5]
I
T1: External Count input to Timer/Counter 1
P3[6]
O
WR#: External Data Memory Write strobe
P3[7]
O
RD#: External Data Memory Read strobe
PSEN#
I/O
Program Store Enable: PSEN# is the Read strobe to External Program Memory. When the
device is executing code from Internal Program Memory, PSEN# is inactive (“H”). When the
device is executing code from External Program Memory, PSEN# is activated twice each
machine cycle, except that two PSEN# activations are skipped during each access to Exter-
nal Data Memory. While the RST input is continually held high (for more than ten machine
cycles), a forced high-to-low input transition on the PSEN# pin will bring the device into the
external host mode programming.
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