參數(shù)資料
型號(hào)： SST85LP1004A-M-C-LBTE
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91
封裝： 12 X 24 MM, 1.30 MM HEIGHT, ROHS COMPLIANT, MO-210, LBGA-91
文件頁(yè)數(shù)： 2/35頁(yè)
文件大?。?/td> 892K
代理商： SST85LP1004A-M-C-LBTE
2009 Silicon Storage Technology, Inc.
S71412-02-000
10/09
10
4 GByte NANDrive
SST85LP1004A
Data Sheet
Configurable Write Protect/Power-down Modes
The WP#/PD# pin can be used for either Write Protect mode or Power-down mode, but only one mode
is active at any time. Either mode can be selected through the host command, Set-WP#/PD#-Mode.
Once the mode is set with this command, the device will stay in the configured mode until the next time
this command is issued. Power-off or reset will not change the configured mode.
Write Protect Mode
When the device is configured in the Write Protect mode, the WP#/PD# pin offers extended data pro-
tection. This feature can be either selected through a jumper or host logic to protect the stored data
from inadvertent system writes or erases, and viruses. The Write Protect feature protects the full
address space of the data stored on the flash media.
In the Write Protect mode, the WP#/PD# pin should be asserted prior to issuing the destructive com-
mands: Erase-Sector, Format-Track, Write-DMA, Write-Multiple, Write-Multiple-without-Erase, Write-
Sector(s), Write-Sector-without-Erase, or Write-Verify. This will force the NANDrive to reject any
destructive commands from the ATA interface. All destructive commands will return 51H in the Status
register and 04H in the Error register signifying an invalid command. All non-destructive commands will
be executed normally.
Power-down Mode
When the device is configured in the Power-down mode, if the WP#/PD# pin is asserted during a com-
mand, the NANDrive completes the current command and returns to the standby mode immediately to
save power. Afterwards, the device will not accept any other commands. Only a Power-on Reset
(POR) or hardware reset will bring the device to normal operation with the WP#/PD# pin de-asserted.
Power-on Initialization
NANDrive is self-initialized during the first power-up. As soon as the power is applied to the NANDrive
it reports busy for typically up to five seconds while performing bad blocks search and low level format.
This initialization is a one time event.
During the first self-initialization, the NANDrive firmware scans all connected flash media devices and
reads their device ID. If the device ID matches the listed flash media devices, the NANDrive performs
drive recognition based on the algorithm provided by the flash media suppliers, including setting up the
bad block table, executing all the necessary handshaking routines for flash media support, and, finally,
performing the low-level format.
If the drive initialization fails, and a visual inspection is unable to determine the problem, SST provides
a comprehensive interface for manufacturing flow debug. This interface not only allows debug of the
failure and manual reset of the initialization process, but also allows customization of user definable
options.
ATA/IDE Interface
The ATA interface can be used for NANDrive manufacturing support. SST provides an example of a
DOS- and Windows-based solution (an executable routine) for manufacturing debug and rework.
相關(guān)PDF資料
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