參數(shù)資料
型號(hào)： SST85LP1004A-M-C-LBTE
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91
封裝： 12 X 24 MM, 1.30 MM HEIGHT, ROHS COMPLIANT, MO-210, LBGA-91
文件頁(yè)數(shù)： 18/35頁(yè)
文件大?。?/td> 892K
代理商： SST85LP1004A-M-C-LBTE
2009 Silicon Storage Technology, Inc.
S71412-02-000
10/09
25
4 GByte NANDrive
SST85LP1004A
Data Sheet
Idle - 97H or E3H
This command causes the NANDrive to set BSY, enter the Idle mode, clear BSY and generate an
interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5 milli-
seconds and the automatic Power-down mode is enabled. If the sector count is zero, the automatic
Power-down mode is also enabled, the timer count is set to 3, with each count being 5 ms. Note that
this time base (5 msec) is different from the ATA specification.
Set-Sleep-Mode - 99H or E6H
This command causes the NANDrive to set BSY, enter the Sleep mode, clear BSY and generate an
interrupt. Recovery from sleep mode is accomplished by simply issuing another command (a reset is
permitted but not required). Sleep mode is also entered when internal timers expire so the host does
not need to issue this command except when it wishes to enter Sleep mode immediately. The default
value for the timer is 15 milliseconds.
Table 11: Transfer Mode Values
Mode
Bits [7:3]
Bits [2:0]
PIO default mode
00000b
000b
PIO default mode, disable IORDY
00000b
001b
PIO flow control transfer mode
00001b
mode1
1. Mode = transfer mode number, all other values are not valid
Multi-word DMA mode
00100b
mode1
Ultra-DMA mode
01000b
mode1
Reserved
Other
N/A
T11.1 1412
Bit ->
76
54321
0
Command (7)
97H or E3H
C/D/H (6)
XDrive
X
Cyl High (5)
X
Cyl Low (4)
X
Sec Num (3)
X
Sec Cnt (2)
Timer Count (5 msec increments)
Feature (1)
X
Bit ->
7
6543210
Command (7)
99H or E6H
C/D/H (6)
XDrive
X
Cyl High (5)
X
Cyl Low (4)
X
Sec Num (3)
X
Sec Cnt (2)
X
Feature (1)
X
相關(guān)PDF資料
PDF描述
SST85LP1004B-M-C-LFTE IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91
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