參數(shù)資料
型號: SST85LD1004T-60-RI-LBTE
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: 存儲控制器/管理單元
英文描述: IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91
封裝: 12 X 24 MM, ROHS COMPLIANT, MO-210, LBGA-91
文件頁數(shù): 4/11頁
文件大?。?/td> 204K
代理商: SST85LD1004T-60-RI-LBTE
2
Fact Sheet
4 GByte NANDrive
SST85LD1004T
2008 Silicon Storage Technology, Inc.
S71394(01)-00-000
09/08
1.0 GENERAL DESCRIPTION
Each NANDrive contains an integrated ATA Controller and
one or more NAND Flash dice in a LBGA package. Refer
to Figure 2-1 for the NANDrive block diagram.
1.1 Performance-optimized NANDrive
The heart of the NANDrive is the ATA Flash Disk Controller
which translates standard ATA signals into flash media data
and control signals. The following components contribute to
the NANDrive’s operation.
1.1.1 Microcontroller Unit (MCU)
The MCU translates ATA/IDE commands into data and
control signals required for flash media operation.
1.1.2 Internal Direct Memory Access (DMA)
The NANDrive uses internal DMA allowing instant data
transfer from buffer to flash media. This implementation
eliminates microcontroller overhead associated with the
traditional, firmware-based approach, thereby increasing
the data transfer rate.
1.1.3 Power Management Unit (PMU)
The
power
management
unit
controls
the
power
consumption of the NANDrive. The PMU dramatically
reduces the power consumption of the NANDrive by
putting the part of the circuitry that is not in operation into
sleep mode.
The Flash File System handles inadvertent power
interrupts and has auto-recovery capability to insure
NANDrive
firmware
integrity.
For
regular
power
management, the Host must send an Idle_Immediate
command and wait for command ready before powering
down the NANDrive.
1.1.4 SRAM Buffer
A key contributor to the NANDrive performance is an
SRAM buffer. The buffer optimizes the host’s data transfer
to and from the flash media.
1.1.5 Embedded Flash File System
The embedded flash file system is an integral part of the
NANDrive. It contains MCU firmware that performs the
following tasks:
1. Translates host side signals into flash media
writes and reads.
2. Provides flash media wear leveling to spread the
flash writes across all memory address space to
increase the longevity of flash media.
3. Keeps track of data file structures.
1.1.6 Error Correction Code (ECC)
High performance is achieved through optimized hardware
error detection and correction.
1.1.7 Serial Communication Interface (SCI)
The Serial Communication Interface (SCI) is designed for
manufacturing error reporting. Always provide access to
the SCI interface in the PCB design to aid in design
validation.
1.1.8 Multi-tasking Interface
The multi-tasking interface enables fast, sustained write
performance by allowing concurrent Read, Program, and
Erase operations to multiple flash media devices.
1.2 Advanced NAND Management
Technology
Advanced NAND management technology balances the
wear on erased blocks with an advanced wear-leveling
scheme which provides a minimum of 100 million product
write cycles. Advanced NAND management technology
tracks the number of program/erase cycles within a group.
When the host updates data, higher priority is given to the
less frequently written erase blocks; thereby, evenly
distributing host writes within a wear-leveling group.
Advanced NAND management technology enhances
NANDrive security with password protection and four
independent protection zones which can be set to Read-
only or Hidden.
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