參數(shù)資料
型號(hào)： SST55VD020-60-C-MVWE
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA85
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-225, VFBGA-85
文件頁(yè)數(shù)： 8/45頁(yè)
文件大?。?/td> 666K
代理商： SST55VD020-60-C-MVWE
16
Data Sheet
NAND Controller
SST55VD020
2009 Silicon Storage Technology, Inc.
S71355-03-000
07/09
SOFTWARE INTERFACE
NAND Controller Drive Register Set Definitions and Protocol
This section defines the drive registers for the NAND Controller and the protocol used to address them.
NAND Controller Addressing
The I/O decoding for an NAND Controller is shown in Table 6.
NAND Controller Registers
The following section describes the hardware registers used by the host software to issue commands to the NAND Control-
ler. These registers are often collectively referred to as the Task File registers. The registers are only selectable through
CS3FX#, CS1FX#, and A2-A0 signals.
Data Register (Read/Write)
This 16-bit register is used to transfer data blocks between the device data buffer and the host. Data transfer can be per-
formed in PIO mode or DMA mode.
Error Register (Read Only)
This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status reg-
ister. The bits are defined as follows:
Symbol
Function
ICRC / BBK
This bit is set when a Bad Block is detected. During an ultra-DMA transfer, this bit is set
on detection of a CRC error.
UNC
This bit is set when an Uncorrectable Error is encountered.
IDNF
The requested sector ID is in error or cannot be found.
ABRT
This bit is set if the command has been aborted because of an NAND Controller status
condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued. It
is required that the host retry any media access command (such as Read-Sectors and
Write-Sectors) that ends with an error condition.
AMNF
This bit is set in case of a general error.
TABLE
6: Task File Registers
CS3FX#
CS1FX#
A2
A1
A0
Registers
IORD# = 0 (IOWR#=1)
IOWR# = 0 (IORD#=1)
1
0
Data (Read)
Data (Write)
1
0
1
Error
Feature
1
0
1
0
Sector Count
1
0
1
Sector Number (LBA 7-0)
1
0
1
0
Cylinder Low (LBA 15-8)
1
0
1
0
1
Cylinder High (LBA 23-16)
1
0
1
0
Drive/Head
1
0
1
Status
Command
0
1
0
Alternate Status
Device Control
T0-0.0 1355
D7
D6
D5
D4
D3
D2
D1
D0
Reset Value
ICRC/BBK
UNC
0
IDNF
0
ABRT
0
AMNF
0000 0000b
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