參數(shù)資料
型號(hào): SST55VD020-60-C-MVWE
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA85
封裝: 6 X 6 MM, ROHS COMPLIANT, MO-225, VFBGA-85
文件頁(yè)數(shù): 5/45頁(yè)
文件大?。?/td> 666K
代理商: SST55VD020-60-C-MVWE
Data Sheet
NAND Controller
SST55VD020
2009 Silicon Storage Technology, Inc.
S71355-03-000
07/09
13
CONFIGURABLE WRITE PROTECT/POWER-DOWN MODES
The WP#/PD# pin can be used for either Write Protect mode or Power-down mode, but only one mode is active at any time.
Either mode can be selected through the host command, Set-WP#/PD#-Mode, explained in Section .
Once the mode is set with this command, the pin will stay in the configured mode until the next time this command is issued.
Power-off or reset will not change the configured mode.
Write Protect Mode
When the WP#/PD# pin is configured in the Write Protect mode, the pin offers extended data protection. This feature can be
either selected through a jumper or host logic to protect the stored data from inadvertent system writes or erases, and
viruses. The Write Protect feature protects the full address space of the data stored on the flash media.
In the Write Protect mode, the WP#/PD# pin should be asserted prior to issuing the destructive commands: Erase-Sector,
Format-Track, Write-DMA, Write-Long-Sector, Write-Multiple, Write-Multiple-without-Erase, Write-Sector(s), Write-Sector-
without-Erase, or Write-Verify. This will force the NAND Controller to reject any destructive commands from the ATA interface.
All destructive commands will return 51H in the Status register and 04H in the Error register signifying an invalid command.
All non-destructive commands will be executed normally.
Power-down Mode
When the WP#/PD# is configured in the Power-down mode, if the pin is asserted during a command, the ATA disk controller
completes the current command and returns to the standby mode immediately to save power. Afterwards, the device will not
accept any other commands. Only a Power-on Reset (POR) or hardware reset will bring the device to normal operation with
the WP#/PD# pin de-asserted.
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