參數(shù)資料
型號(hào): SST55LD017D-40-C-TQWE
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PQFP100
封裝: TQFP-100
文件頁(yè)數(shù): 47/59頁(yè)
文件大?。?/td> 702K
代理商: SST55LD017D-40-C-TQWE
EOL Product Document
ATA Flash Disk Controller
SST55LD017D
51
2006 Silicon Storage Technology, Inc.
S71225-01-EOL
4/06
13.2 Reference Design Schematics
FIGURE
13-1: SCHEMATIC FOR ATA FLASH MODULE, UP TO 640 MBYTE
Optional
header
or
PCB
pads
for
Serial
Communication
Interface
(SCI)
R/B#
NAND
FLASH
CE#
U9
R/B#
U6
CE#
NAND
FLASH
NAND
FLASH
NAND
FLASH
R/B#
CE#
NAND
FLASH
R/B#
U8
U7
R1=620ohm
C2=10pF
at
most
4
dual-die
NAND
flash
chips
are
used
5
dual-die
NAND
flash
chips
are
used
Optional
circuit
for
external
clock.
Remove
R9,
R10
and
stuff
R7,
R8
if
this
circuit
is
used.
External
clock
is
required
if
more
than
4
dual-die
chips
are
assembled
on
the
PCB.
See
below
for
correct
external
clock
RC
values.
R1=487ohm
C2=10pF
Install
either
U2
or
R5
U3
or
U4
circuitry
is
not
needed
for
low
voltage
ADM.
Thus
R6
is
used
to
bypass
the
DC/DC
converter.
Do
not
stuff
R6
and
U3
or
U4
circuitry
together!
DASP#
CSEL
INTRQ
FAD3
D2
D10
FRE#
IOIS16#
FCLE
D4
D11
FAD1
D1
D9
CS1FX#
WP_PD#
D13
RESET#
FALE
FAD6
FAD2
D[15:0]
PDIAG#
FAD7
FAD0
IORD#
CS3FX#
D14
FWE#
FAD5
D3
FAD4
D0
D12
INTClkEn#
IOWR#
D15
D6
D5
D7
D8
SCIDin
SCIDout
SCICLK
D[15:0]
D3
D12
D2
D11
D5
D6
D8
D0
D10
D15
D9
D1
D7
D4
D14
D13
A2
A1
A0
FRDY#
FCE2#
FCE3#
FCE1#
FCE4#
EXTClkIn
EXTClkOut
POR#
GND
OUT
1
OUT
2
FLAG
3
GND
4
BYP
5
GND
6
EN
7
IN
8
1
2
3
4
5
SCIDout
1
SCIDin
2
SCICLK
3
DNU
4
VSS(IO)
5
DNU
6
DNU
7
DNU
8
DNU
9
DNU
10
DNU
11
DNU
12
DNU
13
VDD(IO)
14
DNU
15
DNU
16
DNU
17
DNU
18
VSS(IO)
19
INTClkEn#
20
DNU
21
DNU
22
VDD(CORE)
23
POR#
24
FWP#
25
VSS
(CORE)
26
FRDYbsy#
27
FRE#
28
FWE#
29
FCLE
30
FALE
31
FAD0
32
FAD1
33
FAD2
34
VSS
(IO)
35
EXTClkIn
36
EXTClkOut
37
VDD
(IO)
38
FAD3
39
FAD4
40
FAD5
41
FAD6
42
FAD7
43
VSS
(IO)
44
FCE0#
45
FCE2#
47
FCE3#
48
FCE4#
49
FCE5#
50
D3
51
D11
52
D4
53
D12
54
VSS(IO)
55
D5
56
D13
57
D6
58
D14
59
VDDq(IO)
60
CSEL
61
WP_PD#
62
DASP#
63
VSS(IO)
64
INTRQ
65
CS1FX#
66
CS3FX#
67
TIE_DN
68
TIE_DN
69
IORD#
70
TIE_DN
71
VSS(CORE)
72
IOWR#
73
TIE_DN
74
TIE_UP
75
FCE1#
46
D10
100
D2
99
D9
98
D1
97
VSS
(IO)
96
D8
95
D0
94
D7
93
D15
92
VDDq
(IO)
91
IOCS16#
90
PDIAG#
89
VSS
(IO)
88
DNU
87
TIE_UP
86
A0
85
A1
84
A2
83
TIE_DN
82
RESET#
81
TIE_DN
80
TIE_DN
79
VDDq
(IO)
78
TIE_DN
77
TIE_DN
76
CSEL
WP#
DASP#
INTRQ
CS1FX#
CS3FX#
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
RESET#
A2
A1
A0
PDIAG#
IOCS16#
IORD#
IOWR#
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CE#
ALE
CLE
WE#
WP#
RE#
R/B#
SE#
VSS
VCC
IN
1
GND
2
SHDN#
3
BYP
4
OUT
5
Out
1
Vdd
2
NC
3
Vss
4
U3
TC1269
R7
0
C11
470pF
C10
1.0uF
+
R1
620
R8
0
C12
0.1uF
C2
10pF
C6
0.1uF
SCI
HEADER
U1
SST55LD017D
R3
390
R10
0
HOST
INTERFACE
U5
R9
0
C8
0.1uF
C7
0.1uF
C9
0.1uF
C5
0.1uF
C4
0.1uF
R5
0
R6
0
R2
27K
C3
0.1uF
U4
TC1185
C1
10uF
R4
100K
U2
S-808
VCC
PWR
VCC
PWR
VCC
VDD
VCC
PWR
VCC
1225S01.0
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