參數(shù)資料
型號: SST55LC100-45-C-BWE
元件分類: 存儲控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PBGA84
封裝: ROHS COMPLIANT, MO-210, TFBGA-84
文件頁數(shù): 18/80頁
文件大小: 758K
代理商: SST55LC100-45-C-BWE
Advance Information
CompactFlash Card Controller
SST55LC100
2005 Silicon Storage Technology, Inc.
S71298-00-000
10/05
25
9.1.2 Contiguous I/O Mapped Addressing
When the system decodes a contiguous block of I/O registers to select the CompactFlash card, the registers are
accessed in the block of I/O space decoded by the system as follows:
Note: Address lines which are not indicated are ignored by the CompactFlash card for accessing all the registers in this table.
TABLE
9-3: CONTIGUOUS I/O DECODING
REG#
A3
A2
A1
A0
Offset
IORD#=0
IOWR#=0
Notes
0
0000
0
Even RD Data
Even WR Data
1
1. Register 0 is accessed with CE1# low and CE2# low (and A0 = Don’t Care) as a word register on the combined Odd Data Bus and
Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with CE1# low and CE2#
high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that
lie at offset 1. When accessed twice as byte register with CE1# low, the first byte to be accessed is the Even Byte of the word and the
second byte accessed is the Odd Byte of the equivalent word access. A byte access to register 0 with CE1# high and CE2# low
accesses the error (read) or feature (write) register.
0
0001
1
Error
Features
2
2. Registers at offset 8, 9, and D are non-overlapping duplicates of the registers at offset 0 and 1.
Register 8 is equivalent to register 0, while register 9 accesses the Odd Byte. Therefore, if the registers are byte accessed in the
order 9 then 8 the data will be transferred Odd Byte then Even Byte.
Repeated byte accesses to register 8 or 0 will access consecutive (Even then Odd) Bytes from the data buffer. Repeated word
accesses to register 8, 9, or 0 will access consecutive words from the data buffer. Repeated byte accesses to register 9 are not sup-
ported. However, repeated alternating byte accesses to registers 8 then 9 will access consecutive (Even then Odd) Bytes from the
data buffer. Byte accesses to register 9 access only the Odd Byte of the data.
0
0010
2
Sector Count
0
0011
3
Sector No.
0
0100
4
Cylinder Low
0
0101
5
Cylinder High
0
0110
6
Select Card/Head
0
0111
7
Status
Command
0
1000
8
Dup. Even RD Data
Dup. Even WR Data
0
1001
9
Dup. Odd RD Data
Dup. Odd WR Data
0
1101
D
Dup. Error
Dup. Features
0
1110
E
Alt Status
Device Ctl
0
1111
F
Drive Address
Reserved
T9-3.0 1298
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