參數(shù)資料
型號(hào)： SST49LF004B-33-4C-NH
廠商： SILICON STORAGE TECHNOLOGY INC
元件分類： PROM
英文描述： 4 Mbit LPC Firmware Flash
中文描述： 512K X 8 FLASH 3V PROM, 11 ns, PQCC32
封裝： PLASTIC, MS-016AE, LCC-32
文件頁數(shù)： 21/39頁
文件大?。?/td> 460K
代理商： SST49LF004B-33-4C-NH
Data Sheet
4 Mbit LPC Firmware Flash
SST49LF004B
21
2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
Data# Polling (DQ
7
)
When the SST49LF004B device is in the internal Program
operation, any attempt to read DQ
7
will produce the com-
plement of the true data. Once the Program operation is
completed, DQ
7
will produce true data. Note that even
though DQ
7
may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid. Valid data will appear on
the entire data bus in subsequent successive Read cycles
after an interval of 1 μs. During an internal Erase operation,
any attempt to read DQ
7
will produce a '0'. Once the inter-
nal Erase operation is completed, DQ
7
will produce a '1'.
Data# Polling is valid after the rising edge of the fourth WE#
pulse for the Program operation. For Sector-Erase, Block-
Erase, or Chip-Erase, the Data# Polling is valid after the ris-
ing edge of the sixth WE# pulse. See Figure 15 for Data#
Polling timing diagram. Proper status will not be given using
Data# Polling if the address is in the invalid range.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating '0's
and '1's, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of the fourth WE#
pulse for Program operation. For Sector-Erase, Block-
Erase or Chip-Erase, the Toggle Bit is valid after the rising
edge of the sixth WE# pulse. See Figure 16 for Toggle Bit
timing diagram.
Data Protection (PP Mode)
The SST49LF004B device provides both hardware and
software features to protect nonvolatile data from inadvert-
ent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, WE# high will inhibit
the Write operation. This prevents inadvertent writes during
power-up or power-down.
Software Data Protection (SDP)
The SST49LF004B provides the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tion, i.e., Program and Erase. Any Program operation
requires the inclusion of a series of three-byte sequence.
The three-byte load sequence is used to initiate the Pro-
gram operation, providing optimal protection from inadvert-
ent Write operations, e.g., during the system power-up or
power down. Any Erase operation requires the inclusion of
a five-byte load sequence.
TABLE 12: O
PERATION
M
ODES
S
ELECTION
(PP M
ODE
)
Mode
Read
Program
Erase
RST#
V
IH
V
IH
V
IH
OE#
V
IL
V
IH
V
IH
WE#
V
IH
V
IL
V
IL
DQ
D
OUT
D
IN
X
1
Address
A
IN
A
IN
Sector or Block address,
XXH for Chip-Erase
X
X
A
18
- A
1
= V
IL
, A
0
= V
IL
A
18
- A
1
= V
IL
, A
0
= V
IH
Reset
Write Inhibit
Product Identification
V
IL
V
IH
V
IH
X
V
IL
V
IL
X
High Z
High Z/D
OUT
Manufacturer’s ID (BFH)
Device ID (60H)
V
IH
V
IH
T12.0 1232
1. X can be V
IL
or V
IH
, but no other value.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SST49LF004B-33-4C-NHE 功能描述:閃存 512K X 8 33ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
SST49LF004B334CNHT 制造商:SST 功能描述:NEW
SST49LF004B-33-4C-WHE 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit Firmware Hub
SST49LF004C 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit / 8 Mbit LPC Serial Flash
SST49LF004C-33-4C-NHE 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit / 8 Mbit LPC Serial Flash
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