參數(shù)資料
型號(hào): SST49LF004A
廠商: Silicon Storage Technology, Inc.
英文描述: 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
中文描述: 2兆位/ 3兆/ 4兆位/ 8兆固件集線器
文件頁數(shù): 17/36頁
文件大小: 412K
代理商: SST49LF004A
Advance Information
2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
17
2001 Silicon Storage Technology, Inc.
S71161-06-000
9/01
504
TABLE
8: P
IN
D
ESCRIPTION
Symbol
A
10
-A
0
Pin Name
Address
Type
1
I
Interface
PP
X
Functions
Inputs for low-order addresses during Read and Write operations.
Addresses are internally latched during a Write cycle. For the pro-
gramming interface, these addresses are latched by R/C# and share
the same pins as the high-order address inputs.
To output data during Read cycles and receive input data during
Write cycles. Data is internally latched during a Write cycle. The out-
puts are in tri-state when OE# is high.
To gate the data output buffers
To control the Write operations
This pin determines which interface is operational. When held high,
programmer mode is enabled and when held low, FWH mode is
enabled. This pin must be setup at power-up or before return from
reset and not change during device operation. This pin is internally
pulled- down with a resistor between 20-100 K
.
This is the second reset pin for in-system use. This pin is internally
combined with the RST# pin; If this pin or RST# pin is driven low,
identical operation is exhibited.
These four pins are part of the mechanism that allows multiple parts
to be attached to the same bus. The strapping of these pins is used
to identify the component.The boot device must have ID[3:0]=0000
and it is recommended that all subsequent devices should use
sequential up-count strapping. These pins are internally pulled-down
with a resistor between 20-100 K
.
These individual inputs can be used for additional board flexibility.
The state of these pins can be read through GPI_REG register.
These inputs should be at their desired state before the start of the
PCI clock cycle during which the read is attempted, and should
remain in place until the end of the Read cycle. Unused GPI pins
must not be floated.
When low, prevents programming to the Boot Block sectors at top of
memory. When TBL# is high it disables hardware write protection for
the top block sectors. This pin cannot be left unconnected.
I/O Communications
To provide a clock input to the control unit
Input Communications
To reset the operation of the device
When low, prevents programming to all but the highest addressable
blocks. When WP# is high it disables hardware write protection for
these blocks. This pin cannot be left unconnected.
Select For the Programming interface, this pin determines whether
the address pins are pointing to the row addresses, or to the column
addresses.
These pins must be left unconnected.
To provide power supply (3.0-3.6V)
Circuit ground (OV reference) Every V
SS
pin must be grounded.
Unconnected pins
FWH
DQ
7
-DQ
0
Data
I/O
X
OE#
WE#
IC
Output Enable
Write Enable
Interface
Configuration Pin
I
I
I
X
X
X
X
INIT#
Initialize
I
X
ID[3:0]
Identification Inputs
I
X
FGPI[4:0]
General Purpose Inputs
I
X
TBL#
Top Block Lock
I
X
FWH[3:0]
CLK
FWH4
RST#
WP#
FWH I/Os
Clock
FWH Input
Reset
Write Protect
I/O
I
I
I
I
X
X
X
X
X
X
R/C#
Row/Column Select
I
X
RES
V
DD
V
SS
NC
Reserved
Power Supply
Ground
No Connection
X
X
X
X
I
I
I
X
X
X
T8.3 504
1. I = Input, O = Output
相關(guān)PDF資料
PDF描述
SST49LF004A-33-4C-NH 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF004A-33-4C-WH 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF008A 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF008A-33-4C-NH 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
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參數(shù)描述
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