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參數(shù)資料
| 型號： | SST39VF320-70-4I-B3KE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | PROM |
| 英文描述： | 64 Mbit (x16) Multi-Purpose Flash Plus |
| 中文描述： | 2M X 16 FLASH 2.7V PROM, 70 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 0.80 MM PITCH, LEAD FREE, MO-210AB-1, TFBGA-48 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 302K |
| 代理商： | SST39VF320-70-4I-B3KE |
Preliminary Specifications
32 Mbit Multi-Purpose Flash
SST39VF320
3
2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Data# Polling (DQ
7
)
When the SST39VF320 are in the internal Program opera-
tion, any attempt to read DQ
7
will produce the complement
of the true data. Once the Program operation is completed,
DQ
7
will produce true data. Note that even though DQ
7
may have valid data immediately following the completion
of an internal Write operation, the remaining data outputs
may still be invalid: valid data on the entire data bus will
appear in subsequent successive Read cycles after an
interval of 1 μs. During internal Erase operation, any
attempt to read DQ
7
will produce a ‘0’. Once the internal
Erase operation is completed, DQ
7
will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector-, Block- or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling
timing diagram and Figure 17 for a flowchart.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The Toggle Bit is valid after the rising edge of
fourth WE# (or CE#) pulse for Program operation. For Sec-
tor-, Block- or Chip-Erase, the Toggle Bit is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 7 for
Toggle Bit timing diagram and Figure 17 for a flowchart.
Data Protection
The SST39VF320 provide both hardware and software fea-
tures to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39VF320 provide the JEDEC approved Soft-
ware Data Protection scheme for all data alteration oper-
ations, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion
of six-byte sequence. This group of devices are shipped
with the Software Data Protection permanently enabled.
See Table 4 for the specific software command codes.
During SDP command sequence, invalid commands will
abort the device to Read mode within T
RC
. The contents of
DQ
15
-DQ
8
can be V
IL
or V
IH
, but no other value, during any
SDP command sequence.
Common Flash Memory Interface (CFI)
The SST39VF320 also contain the CFI information to
describe the characteristics of the device. In order to
enter the CFI Query mode, the system must load the
three-byte sequence, similar to the Software ID Entry com-
mand. The last byte cycle of this command loads 98H (CFI
Query command) to address 5555H. Once the device
enters the CFI Query mode, the system can read CFI
data at the addresses given in Tables 5 through 7. The
system must write the CFI Exit command to return to
Read mode from the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices as
the SST39VF320 and manufacturer as SST. This mode
may be accessed by software operations. Users may use
the Software Product Identification operation to identify
the part (i.e., using the device ID) when using multiple
manufacturers in the same socket. For details, see Table
4 for software operation, Figure 11 for the Software ID
Entry and Read timing diagram, and Figure 18 for the
Software ID Entry command sequence flowchart.
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
TABLE
1: P
RODUCT
I
DENTIFICATION
Address
0000H
Data
00BFH
Manufacturer’s ID
Device ID
SST39VF320
0001H
2783H
T1.1 1143
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| SST39VF400A-70-4C-B3K | 功能描述:閃存 256K X 16 70ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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| SST39VF400A-70-4C-B3KE-T | 功能描述:閃存 4M (256Kx16) 70ns 2.7-3.6V Commercial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST39VF400A-70-4C-C1QE | 功能描述:閃存 2.7V to 3.6V 4Mb Multi-Purpose 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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