參數(shù)資料
型號(hào)： SST34HF3223B-70-4C-LP
英文描述： MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|56PIN|PLASTIC
中文描述： 混合存儲(chǔ)器|靜態(tài)存儲(chǔ)器EEPROM中|的CMOS | BGA封裝| 56PIN |塑料
文件頁(yè)數(shù)： 21/32頁(yè)
文件大?。?/td> 486K
代理商： SST34HF3223B-70-4C-LP
Data Sheet
16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory
SST34HF1621 / SST34HF1641
21
2001 Silicon Storage Technology, Inc.
S71172-05-000
10/01 523
FIGURE 12: F
LASH
WE# C
ONTROLLED
B
LOCK
-E
RASE
T
IMING
D
IAGRAM
FIGURE 13: F
LASH
WE# C
ONTROLLED
S
ECTOR
-E
RASE
T
IMING
D
IAGRAM
523 ILL F10.4
ADDRESS A19-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
5555
2AAA
2AAA
5555
5555
XX55
XX50
XX55
XXAA
XX80
XXAA
BAX
OE#
BEF#
SIX-BYTE CODE FOR BLOCK-ERASE
TWP
Note: This device also supports BEF# controlled Block-Erase operation. The WE# and BEF#
signals are interchageable as long as minimum timings are met. (See Table 15)
BAX = Block Address
X can be VIL or VIH, but no other value.
TBY
RY/BY#
VALID
TBR
TBE
523 ILL F11.4
ADDRESS A19-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
5555
2AAA
2AAA
5555
5555
XX55
XX30
XX55
XXAA
XX80
XXAA
SAX
OE#
BEF#
SIX-BYTE CODE FOR SECTOR-ERASE
TSE
TWP
Note: This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF#
signals are interchageable as long as minimum timings are met. (See Table 15)
SAX = Sector Address
X can be VIL or VIH, but no other value.
TBY
RY/BY#
VALID
TBR
相關(guān)PDF資料
PDF描述
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SST34HF3223B-70-4E-LP 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|56PIN|PLASTIC
SST34HF3223B-90-4C-LP 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|56PIN|PLASTIC
SST34HF3223B-90-4E-LP 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|56PIN|PLASTIC
SST34HF3243B-70-4C-LP 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|56PIN|PLASTIC
SST34HF3243B-70-4E-LP 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|CMOS|BGA|56PIN|PLASTIC
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