- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365697 > SST34HF1602D-70-4C-L1SE (Silicon Storage Technology, Inc.) 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory PDF資料下載
參數(shù)資料
| 型號： | SST34HF1602D-70-4C-L1SE |
| 廠商： | Silicon Storage Technology, Inc. |
| 元件分類： | 組合存儲器 |
| 英文描述： | 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory |
| 中文描述： | 16兆兆位并行的SuperFlash 2/4/8 SRAM的ComboMemory |
| 文件頁數(shù)： | 4/38頁 |
| 文件大?。?/td> | 488K |
| 代理商： | SST34HF1602D-70-4C-L1SE |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
4
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1602C / SST34HF1622C / SST34HF1642C
SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S
2004 Silicon Storage Technology, Inc.
S71256-00-000
3/04
Flash Write Operation Status Detection
The SST34HF16x2C/D/S provide one hardware and two
software means to detect the completion of a Write (Pro-
gram or Erase) cycle, in order to optimize the system
Write cycle time. The hardware detection uses the
Ready/Busy# (RY/BY#) pin. The software detection
includes two status bits: Data# Polling (DQ
7
) and Toggle
Bit (DQ
6
). The End-of-Write detection mode is enabled
after the rising edge of WE#, which initiates the internal
Program or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), Data# Polling (DQ
7
) or Toggle Bit (DQ
6
) read may be
simultaneous with the completion of the Write cycle. If this
occurs, the system may possibly get an erroneous result,
i.e., valid data may appear to conflict with either DQ
7
or
DQ
6
. In order to prevent spurious rejection, if an erroneous
result occurs, the software routine should include a loop to
read the accessed location an additional two (2) times. If
both reads are valid, then the device has completed the
Write cycle, otherwise the rejection is valid.
Ready/Busy# (RY/BY#)
The SST34HF16x2C/D/S include a Ready/Busy# (RY/
BY#) output signal. RY/BY# is an open drain output pin that
indicates whether an Erase or Program operation is in
progress. Since RY/BY# is an open drain output, it allows
several devices to be tied in parallel to V
DD
via an external
pull-up resistor. After the rising edge of the final WE# pulse
in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
Byte/Word (CIOF)
The device includes a CIOF pin to control whether the
device data I/O pins operate x8 or x16. If the CIOF pin is at
logic “1” (V
IH
) the device is in x16 data configuration: all
data I/0 pins DQ
0
-DQ
15
are active and controlled by BEF#
and OE#.
If the CIOF pin is at logic “0”, the device is in x8 data config-
uration: only data I/O pins DQ
0
-DQ
7
are active and con-
trolled by BEF# and OE#. The remaining data pins DQ
8
-
DQ
14
are at Hi-Z, while pin DQ
15
is used as the address
input A
-1
for the Least Significant Bit of the address bus.
Flash Data# Polling (DQ
7
)
When the devices are in an internal Program operation, any
attempt to read DQ
7
will produce the complement of the
true data. Once the Program operation is completed, DQ
7
will produce true data. During internal Erase operation, any
attempt to read DQ
7
will produce a ‘0’. Once the internal
Erase operation is completed, DQ
7
will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
BEF#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or BEF#) pulse. See Figure 11 for Data# Poll-
ing (DQ
7
) timing diagram and Figure 23 for a flowchart.
Toggle Bits (DQ
6
and DQ
2
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or BEF#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ
6
) is valid after the
rising edge of sixth WE# (or BEF#) pulse. DQ
6
will be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ
6
will
toggle.
An additional Toggle Bit is available on DQ
2
, which can be
used in conjunction with DQ
6
to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ
2
)
is valid after the rising edge of the last WE# (or BEF#)
pulse of a Write operation. See Figure 12 for Toggle Bit tim-
ing diagram and Figure 23 for a flowchart.
Note:
DQ
7,
DQ
6,
and DQ
2
require a valid address when reading
status information.
TABLE
1: W
RITE
O
PERATION
S
TATUS
Status
Normal
Operation
DQ
7
DQ7#
DQ
6
Toggle
DQ
2
RY/BY#
0
Standard
Program
Standard
Erase
Read From
Erase
Suspended
Sector/Block
Read From
Non-Erase
Suspended
Sector/Block
Program
No Toggle
0
Toggle
Toggle
0
Erase-
Suspend
Mode
1
1
Toggle
1
Data
Data
Data
1
DQ7#
Toggle
N/A
0
T1.0 1256
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SST34HF1602D-70-4C-LPE | 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory |
| SST34HF1622D-70-4C-L1PE | 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory |
| SST34HF1682D-70-4C-L1PE | 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory |
| SST34HF1602S-70-4C-L1PE | 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory |
| SST34HF1622S-70-4C-L1PE | 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST34HF1602D-70-4C-LPE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory |
| SST34HF1602D-70-4C-LSE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory |
| SST34HF1602D-70-4E-B1PE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory |
| SST34HF1602D-70-4E-B1SE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory |
| SST34HF1602D-70-4E-L1PE | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。