參數(shù)資料
型號(hào)： SST32HF1682-70-4E-LSE
廠商： SILICON STORAGE TECHNOLOGY INC
元件分類： 存儲(chǔ)器
英文描述： Multi-Purpose Flash Plus + SRAM ComboMemory
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA62
封裝： 8 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MO-210, LFBGA-62
文件頁(yè)數(shù)： 5/36頁(yè)
文件大小： 414K
代理商： SST32HF1682-70-4E-LSE
Preliminary Specifications
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282
SST32HF1622C / SST32HF1642C / SST32HF3242C
5
2005 Silicon Storage Technology, Inc.
S71253-03-000
5/05
Hardware Block Protection
The SST32HFx2/x2C support top hardware block pro-
tection, which protects the top 32 KWord block of the
device. The Boot Block address ranges are described in
Table 2. Program and Erase operations are prevented on
the 32 KWord when WP# is low. If WP# is left floating, it
is internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase oper-
ations on that block.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T
RP
any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of T
RHR
is
required after RST# is driven high before a valid Read can
take place (see Figure 17).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
Flash Software Data Protection (SDP)
The SST32HFx2/x2C provide the JEDEC approved soft-
ware data protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three byte-load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST32HFx2/x2C devices are shipped with the software
data protection permanently enabled. See Table 6 for the
specific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode, within T
RC.
The contents of DQ
15
-DQ
8
can be V
IL
or
V
IH,
but no other value, during any SDP command
sequence.
SRAM Read
The SRAM Read operation of the SST32HFx2/x2C is con-
trolled by OE# and BES1#, both have to be low with WE#
and BES2 high for the system to obtain data from the out-
puts. BES1# and BES2 are used for SRAM bank selection.
OE# is the output control and is used to gate data from the
output pins. The data bus is in high impedance state when
OE# is high. Refer to the Read cycle timing diagram, Fig-
ure 3, for further details.
SRAM Write
The SRAM Write operation of the SST32HFx2/x2C is con-
trolled by WE# and BES1#, both have to be low, BES2
must be high for the system to write to the SRAM. During
the Word-Write operation, the addresses and data are ref-
erenced to the rising edge of either BES1#, WE#, or the
falling edge of BES2 whichever occurs first. The write time
is measured from the last falling edge of BES#1 or WE# or
the rising edge of BES2 to the first rising edge of BES1#, or
WE# or the falling edge of BES2. Refer to the Write cycle
timing diagrams, Figures 4 and 5, for further details.
Product Identification
The Product Identification mode identifies the devices as
the SST32HFx2/x2C and manufacturer as SST.
This
mode may be accessed by software operations only.
The hardware device ID Read operation, which is typi-
cally used by programmers, cannot be used on this
device because of the shared lines between flash and
SRAM in the multi-chip package. Therefore, applica-
tion of high voltage to pin A
9
may damage this device.
Users may use the software Product Identification opera-
tion to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details, see
Tables 5 and 6 for software operation, Figure 14 for the
software ID entry and read timing diagram and Figure 23
for the ID entry command sequence flowchart.
TABLE
2: B
OOT
B
LOCK
A
DDRESS
R
ANGES
Product
Top Boot Block
SST32HF16x2x
SST32HF32x2x
Address Range
0F8000H-0FFFFFH
1F8000H-1FFFFFH
T2.1 1253
TABLE
3: P
RODUCT
I
DENTIFICATION
Address
0000H
Data
BFH
Manufacturer’s ID
Device ID
SST32HF16x2x
SST32HF32x2x
0001H
0001H
234AH
235AH
T3.2 1253
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