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參數(shù)資料
| 型號： | SST32HF1682-70-4E-LSE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | 存儲器 |
| 英文描述： | Multi-Purpose Flash Plus + SRAM ComboMemory |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA62 |
| 封裝： | 8 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MO-210, LFBGA-62 |
| 文件頁數(shù)： | 4/36頁 |
| 文件大?。?/td> | 414K |
| 代理商： | SST32HF1682-70-4E-LSE |
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4
Preliminary Specifications
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282
SST32HF1622C / SST32HF1642C / SST32HF3242C
2005 Silicon Storage Technology, Inc.
S71253-03-000
5/05
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ
7
or DQ
6.
In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Flash Data# Polling (DQ
7
)
When the SST32HFx2/x2C flash memory banks are in the
internal Program operation, any attempt to read DQ
7
will
produce the complement of the true data. Once the Pro-
gram operation is completed, DQ
7
will produce true data.
Note that even though DQ
7
may have valid data immedi-
ately following the completion of an internal Write opera-
tion, the remaining data outputs may still be invalid: valid
data on the entire data bus will appear in subsequent suc-
cessive Read cycles after an interval of 1 μs. During inter-
nal Erase operation, any attempt to read DQ
7
will produce
a ‘0’. Once the internal Erase operation is completed, DQ
7
will produce a ‘1’. The Data# Polling is valid after the rising
edge of the fourth WE# (or BEF#) pulse for Program opera-
tion. For Sector- or Block-Erase, the Data# Polling is valid
after the rising edge of the sixth WE# (or BEF#) pulse. See
Figure 9 for Data# Polling timing diagram and Figure 22 for
a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ
6
)
is valid after the rising edge of sixth WE# (or BEF#) pulse.
DQ
6
will be set to “1” if a Read operation is attempted on an
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ
6
will toggle.
An additional Toggle Bit is available on DQ
2
, which can be
used in conjunction with DQ
6
to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ
2
) is valid after the rising edge of the last WE# (or
BEF#) pulse of Write operation. See Figure 10 for Toggle
Bit timing diagram and Figure 22 for a flowchart.
Note:
DQ
7
and DQ
2
require a valid address when reading
status information.
Flash Memory Data Protection
The SST32HFx2/x2C flash memory bank provides both
hardware and software features to protect nonvolatile data
from inadvertent writes.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the flash Write operation. This prevents
inadvertent writes during power-up or power-down.
TABLE
1: W
RITE
O
PERATION
S
TATUS
Status
Normal
Operation
DQ
7
DQ
7
#
DQ
6
Toggle
DQ
2
Standard
Program
Standard
Erase
Read from
Erase-Suspended
Sector/Block
Read from
Non- Erase-Suspended
Sector/Block
Program
No Toggle
0
Toggle
Toggle
Erase-
Suspend
Mode
1
1
Toggle
Data
Data
Data
DQ
7
#
Toggle
N/A
T1.0 1253
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| SST32HF3242 | Multi-Purpose Flash Plus + SRAM ComboMemory |
| SST32HF3242-70-4C-LFS | Multi-Purpose Flash Plus + SRAM ComboMemory |
| SST32HF3242-70-4C-LFSE | Multi-Purpose Flash Plus + SRAM ComboMemory |
| SST32HF3242-70-4C-LS | Multi-Purpose Flash Plus + SRAM ComboMemory |
| SST32HF162 | Multi-Purpose Flash (MPF) + SRAM ComboMemory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST32HF201 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:Multi-Purpose Flash (MPF) + SRAM ComboMemory |
| SST32HF201-70-4C-L3K | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:Multi-Purpose Flash (MPF) + SRAM ComboMemory |
| SST32HF201-70-4E-L3K | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:Multi-Purpose Flash (MPF) + SRAM ComboMemory |
| SST32HF201-90-4C-L3K | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:Multi-Purpose Flash (MPF) + SRAM ComboMemory |
| SST32HF201-90-4E-L3K | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:Multi-Purpose Flash (MPF) + SRAM ComboMemory |
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