參數(shù)資料
型號(hào): SSM2518CPZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 19/48頁
文件大?。?/td> 0K
描述: IC AMP AUD PWR 2C STER D 20LFCSP
標(biāo)準(zhǔn)包裝: 5,000
類型: D 類
輸出類型: 2 通道(立體聲)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量: 2.5W x 2 @ 4 歐姆
電源電壓: 2.5 V ~ 5.5 V
特點(diǎn): 消除爆音,數(shù)字輸入,I²C,I²S,靜音,短路和熱保護(hù),關(guān)機(jī),音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 20-LFCSP-WQ(4x4)
封裝/外殼: 20-WFQFN 裸露焊盤,CSP
包裝: 帶卷 (TR)
SSM2518
Data Sheet
Rev. A | Page 26 of 48
REGISTER (REG_MAP) DETAILS
SOFTWARE RESET AND MASTER SOFTWARE POWER-DOWN CONTROL REGISTER
Address: 0x00, Reset: 0x05, Name: Reset_Power_Control
Table 13. Bit Descriptions for Reset_Power_Control
Bits
Bit Name
Settings
Description
Reset
Access
7
S_RST
Software Reset. Write 1 to reset all internal blocks, including I2C registers,
to their initial state.
0x0
RW
0
Normal operation
1
Software reset
6
RESERVED
Reserved.
0x0
RW
5
NO_BCLK
Bit Clock Source Selection. Either the MCLK or BCLK pin can be routed
internally to the bit clock.
0x0
RW
0
BCLK pin used as bit clock source. Typical configuration.
1
MCLK pin used as bit clock source. No BCLK pin connection is needed.
[4:1]
MCS
Master Clock Select. This must match the ratio between the input MCLK
frequency and the audio sample rate, as shown in Table 11.
0x2
RW
0000
64 × fS
0001
128 × fS
0010
256 × fS
0011
384 × fS
0100
512 × fS
0101
768 × fS
0110
100 × fS
0111
200 × fS
1000
400 × fS
1001
Reserved
0
SPWDN
Software Master Power-Down. This places all blocks, except the I2C
interface, into a low power state.
0x1
RW
0
Normal operation
1
Software master power-down
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