- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄297426 > SPT9712BIN (FAIRCHILD SEMICONDUCTOR CORP) PARALLEL, WORD INPUT LOADING, 0.013 us SETTLING TIME, 12-BIT DAC, PDIP28 PDF資料下載
參數(shù)資料
| 型號： | SPT9712BIN |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.013 us SETTLING TIME, 12-BIT DAC, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 49K |
| 代理商： | SPT9712BIN |
SPT
4
3/3/98
SPT9712
THEORY OF OPERATION
The SPT9712 uses a segmented architecture incorporating
most significant bit (MSB) decoding. The four MSBs (D1-D4)
are decoded to thermometer code lines to drive 15 discrete
current sinks. For the eight least significant bits (LSBs), D5
and D6 are binary weighted and D7-D12 are applied to the
R-2R network. The 12-bit decoded data is input to internal
master/slave latches. The latched data is input to the switch-
ing network and is presented on the output pins as comple-
mentary current outputs.
TYPICAL INTERFACE CIRCUIT
The SPT9712 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT9712 in
normal circuit operation. The following sections provide de-
scriptions of the pin functions and outlines critical perfor-
mance criteria to consider for achieving optimal device per-
formance.
POWER SUPPLIES AND GROUNDING
The SPT9712 requires the use of a single -5.2 V supply. All
supplies should be treated as analog supply sources. This
means the ground returns of the device should be connected
to the analog ground plane. All supply pins should be by-
passed with .01
F and 10 F decoupling capacitors as close
to the device as possible.
The two grounds available on the SPT9712 are DGND and
AGND. These grounds are not tied together internal to the
device. The use of ground planes is recommended to achieve
the best performance of the SPT9712. All ground, reference
and analog output pins should be tied directly to the DAC
ground plane. The DAC and system ground planes should be
separate from each other and only connected at a single point
through a ferrite bead to reduce ground noise pickup.
DIGITAL INPUTS AND TIMING
The SPT9712 uses single-ended, 10K ECL-compatible in-
puts for data inputs D1-D12 and Latch Enable. It also em-
ploys master/slave latches to simplify digital interface timing
requirements and reduce glitch energy by synchronizing the
current switches. This is an improvement over the AD9712,
which typically requires external latches
for digital input
synchronization.
Referring to figure 1, data is latched into the DAC on the rising
edge of the latch enable clock with the associated setup and
hold times. The output transition occurs after a typical 1 ns
propagation delay and settles to within
±1 LSB in typically
13 ns. Because of the SPT9712’s rising edge-triggering, no
timing changes are required when replacing an AD9712
operating in nontransparent mode.
VOLTAGE REFERENCE
When using the internal reference, Ref Out should be con-
nected to Control Amp In and decoupled with a 0.1
F
capacitor. Control Amp Out should be connected to Ref In
and decoupled to the analog supply. (See figure 2.)
Full-scale output current is determined by Control Amp In and
RSet using the following formula:
IOut (FS) = (Control Amp In / RSet) x 128
(Current out is a constant 128 factor of the
reference current)
The internal reference is typically -1.20 V with a tolerance of
±0.05 V and a typical drift of 50 ppm/°C. If greater accuracy
or temperature stability is required, an external reference can
be utilized.
OUTPUTS
The output of the SPT9712 is comprised of complementary
current sinks, IOut and IOut . The output current levels at either
IOut or IOut are based upon the digital input code. The sum
of the two is always equal to the full-scale output current
minus one LSB.
By terminating the output current through a resistive load to
ground, an associated voltage develops. The effective resis-
tive load (REff) is the output resistance of the device (ROut) in
parallel with the resistive load (RL). The voltage which devel-
ops can be determined using the following formulas:
Control Amp Out = -1.2 V, and RSet = 7.5 k
IOut (FS) = (-1.2 V / 7.5 k) x 128 = -20.48 mA
RL = 51
ROut = 1.0 k
REff = 51 || 1.0 k = 48.52
VOut = REff x IOut (FS) = 48.52 x -20.48 mA
= -0.994 V
The resistive load of the SPT9712 can be modified to incor-
porate a wide variety of signal levels. However, optimal
device performance is achieved when the outputs are equiva-
lently loaded.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SPX-2000 | INDUSTRY LEADERS DEPEND ON US ...FOR SOLUTIONS |
| SPX1083AU-L | 1.2 V-ADJUSTABLE POSITIVE LDO REGULATOR, 1.2 V DROPOUT, PSFM3 |
| SPX1083AU-L-3.3 | 3.3 V FIXED POSITIVE LDO REGULATOR, 1.2 V DROPOUT, PSFM3 |
| SPX1083AU-L-5.0 | 5 V FIXED POSITIVE LDO REGULATOR, 1.2 V DROPOUT, PSFM3 |
| SPX1083U-L-3.3 | 3.3 V FIXED POSITIVE LDO REGULATOR, 1.2 V DROPOUT, PSFM3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPT9712BIP | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:12-BIT, 100 MWPS ECL D/A CONVERTER |
| SPT9713 | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:12-BIT, 100 MWPS TTL D/A CONVERTER |
| SPT9713AIP | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:12-BIT, 100 MWPS TTL D/A CONVERTER |
| SPT9713BIP | 功能描述:數(shù)模轉(zhuǎn)換器- DAC D/A CONVERTER 12-BIT 100MWPS 640mW RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| SPTA 1.5/ 4-5.08 | 制造商:Vishay BCcomponents 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。