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參數(shù)資料
| 型號： | SPT9712BIN |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.013 us SETTLING TIME, 12-BIT DAC, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 49K |
| 代理商： | SPT9712BIN |
SPT
3
3/3/98
SPT9712
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions: All parameters having min/
max specifications are guaranteed. The Test
Level column indicates the specific device test-
ing actually performed during production and
Quality Assurance inspection. Any blank sec-
tion in the data column indicates that the speci-
fication is not tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA=25 °C, and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
ELECTRICAL SPECIFICATIONS
TA = TMIN - TMAX, VEE = -5.2 V, RSET = 7.5 k, Control Amp In = Ref Out, VOUT = 0 V, unless otherwise specified.
TEST
SPT9712A
SPT9712B
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Power Supply Requirements
Negative Supply Voltage
IV
-5.46
-5.2
-4.94
-5.46
-5.2
-4.94
V
Negative Supply Current (-5.2 V)
+25
°C
I
115
140
115
140
mA
Full Temp
VI
148
mA
Nominal Power Dissipation
V
600
mW
Power Supply Rejection Ratio
±5% of VEE
I
30
100
30
100
A/V
External Ref, +25
°C
Voltage Input and Control
Reference Input Impedance
+25
°CV
3
k
Ref. Multiplying Bandwidth
+25
°C
V
40
MHz
Internal Reference Voltage
VI
-1.15
-1.20
-1.25
-1.15
-1.20
-1.25
V
Internal Reference Voltage Drift
V
50
ppm/
°C
Amplifier Input Impedance
+25
°CV
3
M
Amplifier Input Bandwidth
+25
°C
V
1
MHz
Digital Inputs
Logic 1 Voltage
Full Temp.
VI
-1.0
-0.8
-1.0
-0.8
V
Logic 0 Voltage
Full Temp.
VI
-1.7
-1.5
-1.7
-1.5
V
Logic 1 Current
Full Temp.
VI
20
A
Logic 0 Current
Full Temp.
VI
10
A
Input Capacitance
+25
°CV
3
pF
Input Setup Time - tS
+25
°CIV
3
2
3
2
ns
Input Setup Time - tS
Full Temp.
IV
3.5
ns
Input Hold Time - tH
+25
°C
IV
0.5
0
0.5
0
ns
Input Hold Time - tH
Full Temp.
IV
0.5
ns
Latch Pulse Width - tPWL, tPWH
+25
°C
IV
5.0
4.0
5.0
4.0
ns
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