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參數(shù)資料
| 型號： | SPT7883SIR |
| 廠商： | SIGNAL PROCESSING TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 78K |
| 代理商： | SPT7883SIR |
SPT
5
11/21/01
SPT7883
REFERENCES
The SPT7883 can use either an internal or external volt-
age reference. When the digital input EXTREF is high, the
external reference is used. When EXTREF is low, the inter-
nal reference is used.
INTERNAL REFERENCE
The internal references are set at +0.75 V and +1.75 V.
When the internal reference is used, the full-scale range of
the analog input is set at ±1.0 V differential. Do not connect
external references when the internal reference is used.
EXTERNAL REFERENCE
When external references are used, the voltages applied
to the VREF+ and VREF– pins determine the input voltage
range, which is equal to ±(VREF+ – VREF–). Externally gen-
erated reference voltages must be connected to these
pins and should be symmetric about the common mode
voltage (1.2 V).
ANALOG INPUT
The SPT7883 has a differential input that should have a
common mode voltage of 1.2 V. The input voltage range is
determined by the reference voltages, which may be gen-
erated internally or applied externally.
The input of the SPT7883 can be configured in various
ways depending on whether a single-ended or differential,
AC- or DC-coupled input is desired.
AC-coupled input is most conveniently implemented using
a transformer with a center-tapped secondary winding.
The center tap is connected to the CM node, as shown in
figure 1. In order to obtain low distortion, it is important that
the selected transformer does not exhibit core saturation
at full scale. Excellent results are obtained with the Mini-
Circuits T1-6T or T4-6T. Proper termination of the input is
important for input signal purity. A 50
resistor in series
with each input and a small capacitor (typ 27 pF) across
the inputs will attenuate kickback noise from the sample-
and-hold.
If a DC-coupled single-ended input is wanted, a solution
based on operational amplifiers is usually preferred. The
AD8138 is an easy-to-use, single-ended-to-differential
converter. Its data sheet claims –87 dBc @ 20 MHz.
Lower-cost operational amplifiers may be used if the de-
mands are less strict.
CLOCK
In order to preserve accuracy at high input frequency, it is
important that the clock have low jitter and fast rise and fall
times. Rise/fall times should be kept shorter than 2 ns
whenever possible. Overshoot should be minimized. Low
jitter is especially important when converting high-
frequency input signals. Jitter causes the noise floor to rise
proportionally to input signal frequency. The analog input is
sampled at the falling edge of the clock.
Figure 1 – Typical Interface Circuit
+A2.5
100pF
.1
+
OE
BIAS1
BIAS0
INP
INN
VDD
CM
EXTREF
REFP
REFN
CLK
D9
D7
D6
D5
OVDD
GND
D4
D3
D2
D1
D8
D0
SPT7883
50 (T1-6T) or
200 (T4-6T)
+A2.5
+
0.01
0.1
0.1 0.001
0.01
+
0.1
+
OE
10
Mini-Circuits
T1-6T or T4-6T
T1
AIN
+
10
.1
4.7
CLK
Logic
Interface
Circuit
+A2.5
4.7
+A2.5
50
FB1
(Ferrite Bead)
AGND
DGND
Buffer
+D5
OVDD
GND
VDD
GND
EXTREF
50
27 pF
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