參數(shù)資料
型號: SPT7883SIR
廠商: SIGNAL PROCESSING TECHNOLOGIES
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: SSOP-28
文件頁數(shù): 1/8頁
文件大?。?/td> 78K
代理商: SPT7883SIR
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: 719-528-2300
Fax: 719-528-2370
Web Site: http://www.spt.com
e-mail: sales@spt.com
SPT7883
10-BIT, 70 MSPS A/D CONVERTER
PRELIMINARY INFORMATION
NOVEMBER 21, 2001
GENERAL DESCRIPTION
The SPT7883 is a compact, high-speed, low-power 10-bit
monolithic analog-to-digital converter, implemented in a
0.25 m CMOS process. It has 10-bit resolution with 9.67
effective bits and spurious-free dynamic range (SFDR) of
73 dB for video frequency signals. The converter includes
a high bandwidth sample-and-hold. The full-scale range
can be set between ±0.5 V and ±1.5 V. It operates from a
single 2.5 V supply. Its low distortion and high dynamic
range provide the performance needed for demanding
imaging, video, and communications applications.
The bias current level for the ADC is automatically ad-
justed based on the clock input frequency. Hence, the
power dissipation of the device is continuously optimized
for the operating frequency.
The SPT7883 has a pipelined architecture, resulting in low
input capacitance. Digital error correction of the 9 most
significant bits ensures good linearity for input frequencies
approaching Nyquist.
The SPT7883 is available in a 28-lead SSOP package
over the industrial temperature range (–40 to +85 °C).
FEATURES
2.5 V power supply
SNR: 60 dB @IN = 10 MHz, S = 70 MHz;
58 dB @IN = 30 MHz
Low power dissipation: 145 mW @2.5 V;
Sleep mode: 2.6 mW
Sample rate: 10–115 MSPS
Frequency-dependent biasing
Internal sample-and-hold
Differential input
Low input capacitance
9.67 ENOBs @ IN = 10 MHz, S = 70 MHz
SFDR: 73 dB
IP core available
APPLICATIONS
Imaging
Computer scanners
Communications
Set top boxes
Video products
Battery-operated equipment
Portable test equipment
ADC
REFP
REFN
EXTREF BIAS0 BIAS1
INN
INP
CLK
Clock
Circuit
Correction
Logic
CM
OE
Digital
Outputs
BLOCK DIAGRAM
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