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參數資料
| 型號： | SPT7850SCD |
| 廠商： | SIGNAL PROCESSING TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | 0.300 INCH, CERDIP-28 |
| 文件頁數： | 12/12頁 |
| 文件大小： | 95K |
| 代理商： | SPT7850SCD |
SPT
9
2/10/98
SPT7850
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit
shown in figure 5. This circuit provides ESD robustness to
3.5 kV and prevents latch-up under severe discharge condi-
tions without degrading analog transition times.
Figure 4 - Recommended Input Protection Circuit
47
D1
D2
ADC
Buffer
AVDD
+V
-V
D1 = D2 = Hewlett Packard HP5712 or equivalent
Figure 5 - On-Chip Protection Circuit
VDD
Analog
Pad
120
120
POWER SUPPLY SEQUENCING CONSIDERATIONS
All logic inputs should be held low until power to the device
has settled to the specific tolerances. Avoid power decou-
pling networks with large time constants which could delay
VDD power to the device.
CLOCK INPUT
The SPT7850 is driven from a single-ended TTL-input clock.
Because the pipelined architecture operates on the rising
edge of the clock input, the device can operate over a wide
range of input clock duty cycles without degrading the dy-
namic performance. The device's sample rate is 1/2 of the
input clock frequency. (See the timing diagram.)
DIGITAL OUTPUTS
The digital outputs (D0-D10) are driven by a separate supply
(OVDD) ranging from +3 V to +5 V. This feature makes it
possible to drive the SPT7850's TTL/CMOS-compatible out-
puts with the user's logic system supply. The format of the
output data (D0-D9) is straight binary. (See table III.) The
outputs are latched on the rising edge of CLK. These outputs
can be switched into a tri-state mode by bringing EN high.
Table III - Output Data Information
ANALOG INPUT
OVERRANGE
OUTPUT CODE
D10
D9-D0
+F.S. + 1/2 LSB
1
11 1111 1111
+F.S. -1/2 LSB
O
11 1111 111
+1/2 F.S.
O
+1/2 LSB
O
OO OOOO OOO
0.0 V
O
OO OOOO OOOO
( indicates the flickering bit between logic 0 and 1).
OVERRANGE OUTPUT
The OVERRANGE OUTPUT (D10) is an indication that the
analog input signal has exceeded the positive full scale input
voltage by 1 LSB. When this condition occurs, D10 will switch
to logic 1. All other data outputs (D0 to D9) will remain at
logic 1 as long as D10 remains at logic 1. This feature makes
it possible to include the SPT7850 into higher resolution
systems.
EVALUATION BOARD
The EB7850 Evaluation Board is available to aid designers in
demonstrating the full performance of the SPT7850. This
board includes a reference circuit, clock driver circuit, output
data latches and an on-board reconstruction of the digital
data. An application note describing the operation of this
board as well as information on the testing of the SPT7850 is
also available. Contact the factory for price and availability.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SPT7850SCN | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:10-BIT, 20 MSPS, 140 mW A/D CONVERTER |
| SPT7850SCT | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:10-BIT, 20 MSPS, 140 mW A/D CONVERTER |
| SPT7850SIS | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:10-BIT, 20 MSPS, 140 mW A/D CONVERTER |
| SPT7851 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-BIT, 20 MSPS, 79 mW A/D CONVERTER |
| SPT7851SCT | 功能描述:直流/直流開關轉換器 RoHS:否 制造商:STMicroelectronics 最大輸入電壓:4.5 V 開關頻率:1.5 MHz 輸出電壓:4.6 V 輸出電流:250 mA 輸出端數量:2 最大工作溫度:+ 85 C 安裝風格:SMD/SMT |
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