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參數(shù)資料
| 型號(hào)： | SPT5510SIM |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | 16-BIT, 200 MWPS ECL D/A CONVERTER |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 16-BIT DAC, PQFP44 |
| 封裝： | 10 X 10 MM, METRIC, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 61K |
| 代理商： | SPT5510SIM |
5
9/27/00
SPT5510
Wideband decoupling is required for optimum settling per-
formance. This may require several capacitors in parallel,
and series resistors when appropriate, to reduce resonance
effects. Some applications may need only a single capaci-
tor; however, decoupling influences both long- and short-
term settling, so caution is urged. Your application may
require some research to determine the optimum power
supply decoupling network.
DIGITAL INPUTS AND TIMING
Each digital input is buffered, decoded, and then latched
into D flip-flops which drive the output switches. Master-
slave flip-flops are not used; thus, there is only a 1/2 clock
period delay (max) from data change to output change. In
this architecture, clock and data edge speeds (i.e., rise/fall
times) may affect data feedthrough. Using a data edge of
approximately 0.8 ns will cause data feedthrough of about
10 pV-s, while a 5 ns data edge will reduce the feedthrough
to about 4 pV-s. Data lines may include series resistors or
RC filters for edge control if desired.
The clock signal controls when the data is latched into the
flip-flops. When the CLK is high, the DAC is in track mode. A
negative going CLK latches the data. If CLK is held low, the
DAC is in hold mode. See figure 2.
OUTPUTS
The output is comprised of current sinks, R-2R ladder, and
associated parasitics. See figure 3 for an equivalent output
circuit.
The DAC’s full-scale output current when using the internal
reference amplifier is determined by the voltage at pin
AMP
INB
and the R
SET
resistance. It can be found (to within
an LSB) by using the following formula:
I
OUT
FS = (AMP
INB
/R
SET
) x 16
The inputs determine whether the current from each sink
comes from I
OUT
or I
OUT
as follows:
Code (D15 is MSB)
0 (zero scale)
32768 (mid-scale)
65535 (full-scale)
I
OUT
No current
I
OUT
= I
OUT
All current
I
OUT
All current
I
OUT
= I
OUT
No current
Differential outputs facilitate maximum noise rejection and
signal swing. The DAC is trimmed using a current to voltage
(I-V) converter which provides a virtual ground at the out-
puts and includes sense lines to mitigate the impact of bus
drops. Operating into a load other than a virtual ground will
introduce a slight bow at the output. This bow is related to
the current sinks’ finite output impedance and ladder
impedance.
An example circuit using an I-V converter is shown in figure
4. Note that resistor and op-amp self heating over the DAC’s
full-scale range will introduce additional temperature depen-
dence. The op-amp and feedback resistor must both have
very low tempcos if the DAC’s intrinsic gain drift is to be
maintained. A sense line helps reduce wire effects – both IR
loss and temperature drift.
Figure 2 – Timing Diagram
CLK
DATA
I
OUT
t
D
t
H
t
ST
I
OUT
t
S
t
H
= hold time
t
D
= time to output valid
t
S
= setup time
t
ST
= settling time
Figure 3 – Equivalent Output Circuit
10 pF
1.1k
AV
EE
I
OUT
or I
OUT
+
–
+
–
OGND
OGND
OGND
I
OUT
OGND
GND
GND
250
250
BNC
"I
OUT
”
I
OUT
BNC
"I
OUT
"
Figure 4 – I-V Converter
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