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參數(shù)資料
| 型號(hào)： | SPT5420 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 13-BIT, OCTAL D/A CONVERTER |
| 中文描述： | 13位，八D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 118K |
| 代理商： | SPT5420 |
2
6/26/01
SPT5420
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25 °C
Note:
1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, V
CC
= +5.0 V, V
DD
= +11.5 V, V
SS
= –8.0 V, V
REFT
=3.5 V, V
REFB
= –1.5 V, R
L
= +10 k
, C
L
= 50 pF, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT5420
PARAMETERS
MIN
TYP
MAX
UNITS
Accuracy
Resolution
Integral Linearity Error (ILE)
Differential Linearity Error (DLE)
Zero-Scale Error
Full Scale Error
Gain Error
VI
VI
VI
VI
VI
VI
13
Bits
LSB
LSB
mV
mV
mV
–2.0
–1.0
–25
–25
–25
±0.5
±0.3
+2.0
+1.0
+25
+25
+25
Reference Inputs
Input Current
V
REFT1
V
REFB2
IV
VI
VI
±100
+5.0
nA
V
V
0
+3.5
–1.5
–5.0
0
RGND Inputs
DC Input Impedance
Input Range
V
IV
60
k
V
–2.0
2.0
Output Characteristics
Output Swing
3,4
Short Circuit Current
Resistive Load
DC Output Impedance
VI
IV
VI
IV
+7/–3
V
mA
k
15
5
1.0
Digital Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current
Input Capacitance
VI
VI
VI
V
2.4
V
V
μA/pin
pF
0.8
10
–10
10
Supply Voltages
V
CC
........................................................................+6 V
V
DD
...................................................................... +15 V
V
SS
...................................................................... –15 V
Input Voltages
V
REFT
.................................... V
SS
–0.3 V to V
DD
+0.3 V
V
REFB
................................... V
DD
+0.3 V to V
SS
–0.3 V
Digital inputs....................................–0.3 V to V
CC
+0.3 V
Temperature
Operating Temperature .......................... –40 to +85 °C
Storage ................................................ –65 to +150 °C
Notes:
1. V
REFT
< 8 V + (V
SS
x 0.5); e.g., if V
SS
= –8 V, then V
REFT
< 4 V
2. V
REFB
> (V
DD
x 0.5) – 9.5 V; e.g., if V
DD
= 11 V, then V
REFB
> –4 V
3. V
SS
+ 2.5 V
≤
V
OUT
≤
V
SS
+ 16.0 V for 18.5 V
≤
V
DD
– V
SS
≤
20.0 V
V
SS
+ 2.5 V
≤
V
OUT
≤
V
DD
– 2.5 V for V
DD
– V
SS
≤
18.5 V
4. V
OUT
= 2 X (V
REFB
+[V
REFT
– V
REFB
] X
INPUT CODE
8192
)
–
V
RGND
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