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參數(shù)資料
| 型號： | SPT5400SCP |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | 13-BIT, OCTAL VOLTAGE-OUTPUT DAC WITH PARALLEL INTERFACE |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 7 us SETTLING TIME, 13-BIT DAC, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 73K |
| 代理商： | SPT5400SCP |
8
5/15/00
SPT5400
ORDERING INFORMATION
PART NUMBER
SPT5400SCP
TEMPERATURE RANGE
0 to +70
°
C
PACKAGE
44L PLCC
PIN ASSIGNMENTS
V
O
F
V
O
E
V
S
R
A
A
R
V
S
V
O
D
V
O
C
D
D
D
D
D
D
D
D
D
D
A
Top View
44
1
V
OUT
B
V
OUT
A
V
DD
REFAB
AGNDAB
LDAB
LDCD
CS
WR
A2
A1
V
OUT
G
V
OUT
H
V
DD
REFGH
AGNDGH
GND
LDGH
LDEF
D0
D1
D2
C
6
7
17
18
28
29
39
40
PIN FUNCTIONS
Name
CLR
Function
Clear input (active low). Driving this asynchronous
input low sets the content of all latches to 1000hex.
All DAC outputs are reset to AGNDxx.
Analog ground for DAC C and DAC D.
Reference voltage input for DAC C and DAC C.
Bypass to AGNDCD with a 0.1 to 1
μ
F capacitor.
Negative power supply, –5 V (two pins). Connect
both pins to the supply voltage. Bypass each pin to
the system analog ground with a 0.1
μ
F capacitor.
DAC D output voltage.
DAC C output voltage.
DAC B output voltage.
DAC A output voltage.
AGNDCD
REFCD
V
SS
V
OUT
D
V
OUT
C
V
OUT
B
V
OUT
A
V
DD
Positive power supply, +5 V (two pins). Connect
both pins to the supply voltage. Bypass each pin to
the system analog ground with a 0.1
μ
F capacitor.
Reference voltage input for DAC A and DAC B.
Bypass to AGNDAB with a 0.1 to 1
μ
F capacitor.
Analog ground for DAC A and DAC B.
Load input (active low). Driving this asynchronous
input low transfers the contents of the input latches
A and B to the respective DAC latches.
Load input (active low). Driving this asynchronous
input low transfers the contents of the input latches
C and D to the respective DAC latches.
Chip select (active low).
Write input (active low).
WR
along with
CS
load data
into the DAC input latch selected by A0–A2.
Address bit 2.
Address bit 1.
Address bit 0.
Data bits 12–0. (D0 = LSB)
Load input (active low). Driving this asynchronous
input low transfers the contents of the input latches
E and F to the respective DAC latches.
Load input (active low). Driving this asynchronous
input low transfers the contents of the input latches
G and H to the respective DAC latches.
Digital ground.
Analog ground for DAC G and DAC H.
Reference voltage input for DAC G and DAC H.
Bypass to AGNDGH with a 0.1 to 1
μ
F capacitor.
DAC H output voltage.
DAC G output voltage.
DAC F output voltage.
DAC E output voltage.
Reference voltage input for DAC E and DAC F.
Bypass to AGNDEF with a 0.1 to 1
μ
F capacitor.
Analog ground for DAC E and DAC F.
REFAB
AGNDAB
LDAB
LDCD
CS
WR
A2
A1
A0
D12–D0
LDEF
LDGH
GND
AGNDGH
REFGH
V
OUT
H
V
OUT
G
V
OUT
F
V
OUT
E
REFEF
AGNDEF
Name
Function
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR
USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR
THE RIGHTS OF OTHERS.
www.fairchildsemi.com
Copyright 2002 Fairchild Semiconductor Corporation
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