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參數(shù)資料
| 型號(hào)： | SPT5400SCP |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | 13-BIT, OCTAL VOLTAGE-OUTPUT DAC WITH PARALLEL INTERFACE |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 7 us SETTLING TIME, 13-BIT DAC, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 73K |
| 代理商： | SPT5400SCP |
3
5/15/00
SPT5400
TEST LEVEL CODES
All electrical characteristics are subject
to the following conditions:
All parameters having min/max specifi-
cations are guaranteed. The Test Level
column indicates the specific device
testing actually performed during pro-
duction and Quality Assurance inspec-
tion. Any blank section in the data
column indicates that the specification
is not tested at the specified condition.
TEST LEVEL
TEST PROCEDURE
I
100% production tested at the specified temperature.
100% production tested at T
A
= +25
°
C, and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteriza-
tion data.
Parameter is a typical value for information purposes only.
100% production tested at T
A
= +25
°
C. Parameter is guaranteed over
specified temperature range.
II
III
IV
V
VI
Figure 1 – Timing Diagram
t
5
t
1
t
6
t
2
t
9
t
10
t
7
t
8
t
4
t
3
A0–A2
D0–D12
LD
CS
WR
NOTES:
1. All input rise and fall times
are measured from 10% to
90% of +5 V. t
R
= t
F
= 5 ns.
2. If
LD
is activated while
WR
is
low,
LD
must stay low for t
3
or
longer after
WR
goes high.
Table I – Timing Parameters
PARAMETER
CS
Pulse Width Low
WR
Pulse Width Low
LD
Pulse Width Low
CLR
Pulse Width Low
CS
to
WR
Low
CS
High to
WR
High
Data Valid to
WR
Setup
Data Valid to
WR
Hold
Address Valid to
WR
Setup
Address Valid to
WR
Hold
SYMBOL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
MIN TYP MAX
50
50
50
100
0
0
20
0
10
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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