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參數(shù)資料
| 型號(hào)： | SPT5230 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 10-BIT, 36 MWPS TRIPLE VIDEO DAC |
| 中文描述： | 10位，36 MWPS三路視頻DAC |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大小： | 51K |
| 代理商： | SPT5230 |
3
5/1/00
SPT5230
INTERFACE CONSIDERATIONS
Figure 4 shows a typical interface circuit of the SPT5230 in
normal circuit operation.
SUPPLY AND GROUND CONSIDERATIONS
Fairchild suggests that all power supply pins (AV
DD
) be tied
together and decoupled using a 0.1
μ
F ceramic capacitor in
parallel with a 10
μ
F tantalum capacitor.
EXTERNAL REFERENCE VOLTAGE (V
REF1
)
A +3 V (
±
10%) voltage reference should be externally gener-
ated for the V
REF1
pin using the simple voltage divider shown
in figure 4. Connect a 0.1
μ
F bypass capacitor between
V
REF1
and AV
SS
as close to the pin as possible.
EXTERNAL REFERENCE VOLTAGE (V
REF2
)
V
REF2
needs to be externally connected to AV
DD
through a
1.2 k
(5%) resistor. Connect a 0.1
μ
F bypass capacitor
between V
REF2
and AV
SS
as close to the pin as possible.
CONTROL VOLTAGE DECOUPLING (V
CS1
)
This is a decoupling pin for the control voltage internal
circuitry. An external 0.1
μ
F capacitor should be connected
between V
CS1
and AV
SS
as close to the pin as possible.
FULL-SCALE ADJUST CONTROL (V
CS2
)
V
CS2
is an external control voltage input that controls the
peak-to-peak full scale output voltage. This is the only exter-
nal voltage that has direct control over the SPT5230 output
voltage. The voltage output swings between AV
DD
(+5 V) and
a value controlled by V
CS2
.
Assuming that an output load resistor of 75
is connected
between the output and AV
DD
, figure 2 shows what the output
voltage will be for the digital inputs all equal to logic 0, as V
CS2
is varied from 2 V to 4 V. Figure 3 shows the peak-to-peak
output voltage versus V
CS2
and table I shows an example in
which V
CS2
is equal to 2.1 V.
CURRENT OUTPUTS
Each red, green and blue current output should have a load
resistor connected to AV
DD
. The resistors are typically 75
and should be kept in the 72
to 85
range. The outputs
should drive a high impedance load such as a voltage
follower.
OUTPUT LEVEL SHIFTING CIRCUIT
The SPT5230 voltage output will swing from +3.0 V to +4.99
V for V
CS2
= 2.1 V as shown in table I. If level shifting of the
output is desired, Fairchild recommends use of the circuit
shown in figure 5. The desired –FS voltage is fed into the
collector of the emitter to achieve the desired level shift. (Note
the phase inversion that will occur due to the common
emitter.) Choose any appropriate video op amp with ad-
equate power supply head room.
Table I – Binary Codes
1 LSB = 1.953 mV, V
CS2
≈
2.1 V
Digital Input
Analog
Out (V)
Step
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
(MSB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
.
.
.
1
1
1
1
1
1
1
1
1
1
(LSB)
0
0
1
1
0
1
2
3
.
.
.
0
0
0
0
0
0
0
0
0
0
0
0
0 3.000000
1 3.001953
0 3.003906
1 3.005859
.
.
.
1022
1023
1
1
1
1
1
1
1
1
0 4.996094
1 4.998047
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPT5230SCT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| SPT5240 | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:10-bit, 400 MWPS Current Output Digital-to-Analog Converter |
| SPT5240SIT | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 10BIT 400MWPS 3V DaC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| SPT5240SIT_Q | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 10BIT 400MWPS 3V DaC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| SPT5303 | 制造商:SSDI 制造商全稱:Solid States Devices, Inc 功能描述:200 WATT NPN SILICON POWER TRANSISTOR |
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