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參數(shù)資料
| 型號： | SPNZ132 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TMS470 Microcontrollers |
| 中文描述： | TMS470的微控制器 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 96K |
| 代理商： | SPNZ132 |
SPNZ132
A128 Silicon Errata
7
Abort Acknowledge Bit Not Set After Transmission Request Reset
Advisory SCC#7
Description
:
After aborting a message using the Transmission Request Reset (TRR) register bit, there are
some rare instances where the TRR bit will clear without setting the Abort Acknowledge (AA)
bit.
For the rare instance to occur, all three of the following conditions must exist:
1.
The current message has a message error or lost arbitration. This message does not need
to have the same mailbox number as the TRR bit mailbox discussed in condition 2.
2.
The TRS bit of the same mailbox as the TRR mailbox must be set from either this current
message, before the current message and still pending, or just set.
3.
The TRR bit must be set in the exact ICLK cycle were the wrapper state machine is in IDLE
for one cycle. (One ICLK before or after and the condition will not occur). This IDLE state can
occur just after the current message. It can also occur just a few ICLKs after setting the TRS
bit of any mailbox after the current message (point 1 above).
If these conditions occur, then the TRR and TRS bits for the mailbox will clear t
clr
ICLKs after
the TRR bit is set where:
t
clr
= ((16mailbox_number)*2)+3 ICLK cycles
The TA and AA bits will not be set if this condition occurs. Normally, either the TA or AA bit
sets after TRR bit goes to 0.
Workaround
:
When this problem occurs, the TRR and TRS bits will clear within t
clr
ICLK cycles. To check for
this condition, first disable the interrupts. Check the TRR bits’ t
clr
ICLK cycles after setting the
TRR bits to make sure that they are still set. A set TRR bit indicates the problem did not occur.
If TRR is cleared, then perhaps it was the normal end of a message and the TA or AA bits are
set. Check both the TA and AA bits. If they are both 0, then the conditions did occur. Handle
the condition as the interrupt service routine would, except that the AA bit does not need
clearing now. If the TA or AA bit is set, then the normal interrupt routine will happen when the
interrupt is re-enabled.
SPI Clock Must Be Configured to a Faster Baud Rate
Advisory SPI#1
Description
:
When the SPI is operated in slave mode, the SPI clock must be configured to a baud rate as
close to the master’s baud rate as possible. If the baud rate is too slow, the enable signal will
not be generated in time to keep the master from sending additional data. If the baud rate is
too fast, the slave will capture the data before the last bit is shifted in.
Workaround
:
The documentation (literature number SPNU195) has been updated to reflect this
requirement.
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