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參數(shù)資料
| 型號： | SPNZ132 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TMS470 Microcontrollers |
| 中文描述： | TMS470的微控制器 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 96K |
| 代理商： | SPNZ132 |
SPNZ132
A128 Silicon Errata
5
Auto Read Clear Malfunction
Advisory HET#15
Description
:
The HET Auto Read Clear feature does not always work properly. Specifically, the data field of
instruction X is NOT cleared if the following conditions are true at the same time:
1.
The 64-bit CPU read access happens exactly in the two HET time slots PRECEDING the time
slot Y in which instruction X is executed.
2.
Instruction X just changes its data field (in time slot Y). (Example: Instruction X is an ECNT
instruction, which just detected an edge). The malfunction does NOT occur if the data field
of instruction X does not change, since then b) is not true.
Workaround
:
See above.
MCMP Causes a Constant Signal, not PWM
Advisory HET#16
Description
:
MCMP causes a constant signal instead of a PWM, if both of the following conditions are met:
1.
Consecutive compare match in every LRP for order = reg_ge_data (only when [data=0]).
2.
The high resolution delay (in number of SYSCLK cycles) is equal to the time slot the MCM
is executed.
Workaround
:
Replace each MCMP with a twoinstruction sequence: ECMP and MOV32
Write Accesses to the RTICNTR Register May Cause Tap Interrupt
Advisory RTI#3
Description
:
Write accesses to the RTICNTR register will clear the CNTR (21 bit counter), which causes a
Tap interrupt if the corresponding bit switches from a 1 to a 0.
Workaround
:
Disable the RTI before changing the RTICNTR value.
Tap Interrupt When Clearing Counter in Suspend Mode
Advisory RTI#4
Description
:
Write accesses to the RTICNTR register will clear the CNTR (21 bit counter), which causes a
Tap interrupt if the corresponding bit switches from a 1 to a 0 when the suspend signal is
asserted. This is the same problem as RTI#3, however, on the initial fix of RTI#3, the case
where the suspend signal is asserted because an emulator breakpoint was not considered.
This problem occurs when the emulator has set a breakpoint on one of the instructions closely
following the instruction which writes to the counter.
Workaround
:
None
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