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參數(shù)資料
| 型號： | SPMC802B-PD05 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 32-pin General Purpose Microcontroller (OTP) |
| 中文描述： | 32引腳的通用微控制器（檢察官） |
| 文件頁數(shù)： | 9/27頁 |
| 文件大?。?/td> | 1041K |
| 代理商： | SPMC802B-PD05 |
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SPMC802B
5.4. Port D Group
The I/O port D has 4 programmable I/Os that are controlled by
data register PD, direction control register DPD, and pull-up/down
resistance control register RPD. DPD is used to control the pad
I/O attribute. Setting the bit(s) to '1' will enforce the
corresponding pad(s) to output mode. It is a write-only register.
PD is used to store the data contents for output. Reading PD will
get the stored data when corresponding bit of DPD is set as output
mode, or will get the pad status if it is in input mode.
There is a built-in Pull-Up resistor on each pad. These pull-up
resistors can be controlled by users' program through RPD.
The corresponding pads are assigned for SPMC802B as following: (VDD = 5.0V)
PIN
Rp
IN
OUT
Special Function
PD3
100K Up@rpd3
8/8mA
PD2
100K Up@rpd2
8/8mA
PD1
100K Up@rpd1
8/8mA
PD0
100K Up@rpd0
8/8mA
5.5. Interrupt
There are four kinds of interrupt, Software Interrupt, External
Interrupt, Timer Interrupt, and Comparator interrupt. Each of the
last three interrupts has individual status (occurred or not) and
control (enable or not) registers, whereas Software Interrupt does
not. In general, once an interrupt event occurs, the
corresponding flag bit will be set. If the related interrupt control
bit is set to enable interrupt, an interrupt request signal will be
generated and will be dealt with by CPU for service. The
interrupt flag bits must be cleared in the interrupt service routine to
prevent program from deadlock in interrupt service routine.
Software interrupt is generated by the instruction BRK. The BRK
is an executable instruction interrupt; it is executed regardless of
the state of the I-bit in the Processor Status Register Flag (inside
CPU). It jumps to interrupt routine when BRK occurred. As with
any instruction, interrupts pending during the previous instruction
is served.
External interrupts are coming from IRQ0, IRQ1, or IRQ2. These
IRQ signals are combined with the configurable options and
status/control registers to generate the interrupt events to CPU.
For all IRQ channels, each channel has individual interrupt control
or status bits. Once an external interrupt is occurred, the flag will
be set and stays at set unless user software clears the flag. The
interrupt request signal will be generated in case of the interrupt is
enabled. Channel IRQ0 has a configurable option used to set the
trigger mode of the interrupt event. The trigger mode can be
selected as either edge trigger mode or level trigger mode.
When the interrupt channel is enabled with edge trigger mode, an
active transition edge on the external interrupt inputs will generate
the interrupt. If the channel is enabled with level trigger mode,
the active level of the external interrupt inputs will set the interrupt
event until the active level condition is removed. IRQ1 and IRQ2
support edge trigger mode only.
The
external
interrupt
IRQ0
supports
interrupt-flag-bit
auto-clearing function. It is activated only when interrupt
channels of IRQ1 is disabled. When the auto-clearing function is
activated, the flag of IRQ0 will be cleared automatically as soon as
the interrupt vector is accessed. The user software in interrupt
service routine does no need to check the flag because that flag
bit has been cleared by hardware. It is used to simplify the
interrupt service routine only when the IRQ0 is the unique interrupt
source of the system. If the Timer interrupts or Comparator
interrupts are enabled with only IRQ0 being enabled as external
interrupt source, the external interrupt event due to IRQ0 might be
lost in case two interrupt events occur in the same time. To avoid
the problem of IRQ0 loss, using IRQ1 or IRQ2 for external
interrupt channel, instead of using IRQ0, can solve it. However,
no matter the auto-clearing function of interrupt flag is functional,
user software must clear the interrupt occurrence in the interrupt
service routine.
There is a new configurable option, named irqac, to be added for
future supporting. This option can disable the auto-clearing
function of IRQ0 interrupt flag. The program tool to maintain the
body consistency will control it.
In SPMC802B, IRQ0 is come from either PB5 with falling-edge
trigger or group input PA3:0 with rising-edge trigger. A
configurable option is used to activate the group interrupt input on
PA3:0. IRQ1 is come from PA7. IRQ2 is come from external
interrupt group input, PC7:0.
Sunplus Technology Co., Ltd.
Proprietary & Confidential
9
AUG. 07, 2002
Version: 1.0
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相關(guān)代理商/技術(shù)參數(shù) |
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| SPMC802B-PD06 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-pin General Purpose Microcontroller (OTP) |
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| SPMC802B-PD11 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-pin General Purpose Microcontroller (OTP) |
| SPMC802B-PS04 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-pin General Purpose Microcontroller (OTP) |
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