參數(shù)資料
型號: SPC563M64L5COAY
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, LEAD FREE, LQFP-144
文件頁數(shù): 35/140頁
文件大?。?/td> 1310K
代理商: SPC563M64L5COAY
Overview
SPC563M64
Doc ID 14642 Rev 6
Configurable bus speed modes
–Bus monitor
Configurable wait states
System integration unit (SIU)
Centralized GPIO control of 80 I/O pins
Centralized pad control on a per-pin basis
Pin function selection
Configurable weak pull-up or pull-down
Drive strength
Slew rate
Hysteresis
System reset monitoring and generation
External interrupt inputs, filtering and control
Critical Interrupt control
Non-Maskable Interrupt control
Internal multiplexer subblock (IMUX)
Allows flexible selection of eQADC trigger inputs (eTPU, eMIOS and external
signals)
Allows selection of interrupt requests between external pins and DSPI
Error correction status module (ECSM)
Configurable error-correcting codes (ECC) reporting
Single-bit error correction reporting
On-chip flash memory
Up to 1.5 MB flash memory, accessed via a 64-bit wide bus interface
16 KB shadow block
Fetch Accelerator
Provide single cycle flash access @ 80 MHz
Quadruple 128-bit wide prefetch/burst buffers
Prefetch buffers can be configured to prefetch code or data or both
Censorship protection scheme to prevent flash content visibility
Flash divided into two independent arrays, allowing reading from one array while
erasing/programming the other array (used for EEPROM emulation)
Memory block:
For SPC563M64: 18 blocks (4
× 16 KB, 2 × 32 KB, 2 × 64 KB, 10 × 128 KB)
For SPC563M60: 14 blocks (4
× 16 KB, 2 × 32 KB, 2 × 64 KB, 6 × 128 KB)(b)
Hardware programming state machine
On-chip static RAM
For SPC563M64: 94 KB general purpose RAM of which 32 KB are on standby
power supply
b.
Revision 1 of the SPC563M60 has a different flash memory organization: 10 blocks (2
× 16 KB, 2 × 48 KB, 2 ×
64 KB, 2
× 128 KB, 2 × 256 KB).
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