參數(shù)資料
型號: SPC563M64L5COAY
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, LEAD FREE, LQFP-144
文件頁數(shù): 100/140頁
文件大?。?/td> 1310K
代理商: SPC563M64L5COAY
Pin
out
and
signa
lde
scr
ipt
ion
SPC5
63M
64
6
2
/1
Doc
ID
1
4642
R
e
v
6
1.
For each pin in the table, each line in the Function column is a separate function of the pin. For all I/O pins the selection of primary pin function or secondary function or
GPIO is done in the SIU except where explicitly noted.
2.
Values in this column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR number. For example, PCR[190]
refers to the SIU register named SIU_PCR190.
3.
The Pad Configuration Register (PCR) PA field is used by software to select pin function.
4.
The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3 V to 5.0 V range (-
10%/+5%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/- 10%).
5.
Terminology is O - output, I - input, Up - weak pull up enabled, Down - weak pull down enabled, Low - output driven low, High - output driven high. A dash for the function in
this column denotes that both the input and output buffer are turned off.
6.
Function after reset of GPI is general purpose input. A dash for the function in this column denotes that both the input and output buffer are turned off.
7.
The GPIO functions on GPIO206 and GPIO207 can be selected as trigger functions in the SIU for the ADC by making the proper selections in the SIU_ETISR and
SIU_ISEL3 registers in the SIU.
8.
Some signals in this section are available only on calibration package.
9.
On the calibration package, the Nexus function on this pin is enabled when the NEXUSCFG pin is high and Nexus is configured to full port mode. On the 176-pin and 208-
pin packages, the Nexus function on this pin is enabled permanently.
10. In the calibration package, the I/O segment containing this pin is called VDDE12.
11. 208-ball BGA package only
12. When configured as Nexus (208-pin package or calibration package with NEXUSCFG=1), and JCOMP is asserted during reset, MDO[0] is driven high until the crystal
oscillator becomes stable, at which time it is then negated.
13. The function of this pin is Nexus when NEXUSCFG is high.
14. High when the pin is configured to Nexus, low otherwise.
15. O/Low for the calibration with NEXUSCFG=0; I/Up otherwise.
16. ALT_ADDR/Low for the calibration package with NEXUSCFG=0; EVTI/Up otherwise.
17. In 176-pin and 208-pin packages, the Nexus function is disabled and the pin/ball has the secondary function
18. This signal is not available in the 176-pin and 208-pin packages.
19. The primary function is not selected via the PA field when the pin is a Nexus signal. Instead, it is activated by the Nexus controller.
20. TDI and TDO are required for JTAG operation.
21. The primary function is not selected via the PA field when the pin is a JTAG signal. Instead, it is activated by the JTAG controller.
22. The function and state of the CAN_A and eSCI_A pins after execution of the BAM program is determined by the BOOTCFG1 pin.
23. ETPUA[24:29] are input and output. The input muxing is controlled by SIU_ISEL8 register.
24. eTPU_A[25] is an output only function.
25. Only the output channels of eTPU[8:9] are connected to pins.
26. Only the output of eMIOS[12] is connected to the pin. The DSPI_C_SOUT is not available in this device.
27. The function after reset of the XTAL pin is determined by the value of the signal on the PLLCFG[1] pin. When bypass mode is chosen XTAL has no function and should be
grounded.
28. The function after reset of the EXTAL_EXTCLK pin is determined by the value of the signal on the PLLCFG[1] pin. If the EXTCLK function is chosen, the valid operating
voltage for the pin is 1.62 V to 3.6 V. If the EXTAL function is chosen, the valid operating voltage is 3.3 V.
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