t
參數(shù)資料
型號: SPC5607BF1MLU6
廠商: Freescale Semiconductor
文件頁數(shù): 99/112頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 1.5MB FLASH 176LQFP
標(biāo)準(zhǔn)包裝: 200
系列: MPC56xx Qorivva
核心處理器: e200z0h
芯體尺寸: 32-位
速度: 64MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 149
程序存儲器容量: 1.5MB(1.5M x 8)
程序存儲器類型: 閃存
RAM 容量: 96K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 29x10b,5x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 176-LQFP
包裝: 托盤
Electrical
charac
teristics
MPC5607B
M
icr
ocontr
oller
Data
Sheet,
Re
v
.7
Fre
e
scale
Se
mi
condu
cto
r
87
10
tHI
SR D Data hold time for inputs
Master mode
0
0
ns
Slave mode
26
——
——
11
tSUO
7
CC D Data valid after SCK edge Master mode
32
50
ns
Slave mode
52
160
12
tHO
CC D Data hold time for outputs
Master mode
0
0
ns
Slave mode
8
13
1 Operating conditions: C
L = 10 to 50 pF, SlewIN = 3.5 to 15 ns
2 Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK
starts before CSn is asserted. DSPI2 has only SLOW SCK available.
3 Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is
deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.
4 The t
CSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay
between internal CS and internal SCK must be higher than
t
CSC to ensure positive tCSCext.
5 The t
ASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between
internal CS and internal SCK must be higher than
t
ASC to ensure positive tASCext.
6 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.
7 SCK and SOUT are configured as MEDIUM pad.
Table 47. DSPI characteristics1 (continued)
No.
Symbol
C
Parameter
DSPI0/DSPI1/DSPI3/DSPI5
DSPI2/DSPI4
Unit
Min
Typ
Max
Min
Typ
Max
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