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參數(shù)資料
| 型號： | SPC5607BF1MLU6 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 69/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 1.5MB FLASH 176LQFP |
| 標準包裝： | 200 |
| 系列： | MPC56xx Qorivva |
| 核心處理器： | e200z0h |
| 芯體尺寸： | 32-位 |
| 速度： | 64MHz |
| 連通性： | CAN，I²C，LIN，SCI，SPI |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 149 |
| 程序存儲器容量： | 1.5MB（1.5M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 96K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 29x10b，5x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 176-LQFP |
| 包裝： | 托盤 |
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MPC5607B Microcontroller Data Sheet, Rev. 7
Block diagram
Freescale Semiconductor
6
Table 2 summarizes the functions of the blocks present on the MPC5607B.
Table 2. MPC5607B series block summary
Block
Function
Analog-to-digital converter (ADC) Converts analog voltages to digital values
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Clock monitor unit (CMU)
Monitors clock source (internal and external) integrity
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Crossbar switch (XBAR)
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.
Deserial serial peripheral interface
(DSPI)
Provides a synchronous serial interface for communication with external devices
Enhanced direct memory access
(eDMA)
Performs complex data transfers with minimal intervention from a host processor
via “n” programmable channels
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Error correction status module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset status
register, wakeup control for exiting sleep modes, and optional features such as
information on memory errors reported by error-correcting codes
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol
Frequency-modulated
phase-locked loop (FMPLL)
Generates high-speed system clocks and supports programmable frequency
modulation
Inter-integrated circuit (I2C) bus
Two-wire bidirectional serial bus that provides a simple and efficient method of
data exchange between devices
Internal multiplexer (IMUX) SIU
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller (JTAGC)
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Memory protection unit (MPU)
Provides hardware access control for all memory references generated in a
device
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and
modetransition sequences in all functional states; also manages the power
control unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
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