參數(shù)資料
型號： SPC5604CF2MLL6
廠商： Freescale Semiconductor
文件頁數(shù)： 14/109頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 512KB FLASH 100LQFP
標(biāo)準(zhǔn)包裝： 90
系列： MPC56xx Qorivva
核心處理器： e200z0h
芯體尺寸： 32-位
速度： 64MHz
連通性： CAN，I²C，LIN，SCI，SPI
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 79
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 48K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 28x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 100-LQFP
包裝： 托盤
MPC5604B/C Microcontroller Data Sheet, Rev. 11.1
Package pinouts and signal descriptions
Freescale Semiconductor
12
3.3
Voltage supply pins
Voltage supply pins are used to provide power to the device. Three dedicated VDD_LV/VSS_LV supply pairs are used for 1.2
V regulator stabilization.
3.4
Pad types
In the device the following types of pads are available for system pins and functional port pins:
S = Slow1
I = Input only with analog feature1
J = Input/Output (‘S’ pad) with analog feature
X = Oscillator
Table 3. Voltage supply pin descriptions
Port pin
Function
Pin number
64 LQFP1
1 Pin numbers apply to both the MPC560xB and MPC560xC packages.
100 LQFP
144 LQFP
208
MAPBGA2
2 208 MAPBGA available only as development package for Nexus2+
VDD_HV
Digital supply voltage
7, 28, 56
15, 37, 70, 84 19, 51, 100,
123
C2, D9, E16,
G13, H3, N9,
R5
VSS_HV
Digital ground
6, 8, 26, 55
14, 16, 35,
69, 83
18, 20, 49,
99, 122
G7, G8, G9,
G10, H1, H7,
H8, H9, H10,
J7, J8, J9,
J10, K7, K8,
K9, K10
VDD_LV
1.2V decoupling pins. Decoupling
capacitor must be connected between
these pins and the nearest VSS_LV pin.3
3 A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable
voltage (see the recommended operating conditions in the device datasheet for details).
11, 23, 57
19, 32, 85
23, 46, 124
D8, K4, P7
VSS_LV
1.2V decoupling pins. Decoupling
capacitor must be connected between
these pins and the nearest VDD_LV pin.3
10, 24, 58
18, 33, 86
22, 47, 125
C8, J2, N7
VDD_BV
Internal regulator supply voltage
12
20
24
K3
VSS_HV_ADC Reference ground and analog ground for
the ADC
33
51
73
R15
VDD_HV_ADC Reference voltage and analog supply for
the ADC
34
52
74
P14
1. See the I/O pad electrical characteristics in the device datasheet for details.
2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see PCR.SRC
in section Pad Configuration Registers (PCR0–PCR122) in the device reference manual).
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