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參數(shù)資料
| 型號： | SPC5200CVR400R2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 41/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 400MHZ 272-PBGA |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | MPC52xx |
| 處理器類型： | 32-位 MPC52xx PowerPC |
| 速度： | 400MHz |
| 電壓： | 1.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 272-BBGA |
| 供應(yīng)商設(shè)備封裝： | 272-PBGA（27x27） |
| 包裝： | 帶卷 (TR) |
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MPC5200B Data Sheet, Rev. 4
46
Freescale Semiconductor
NOTE
Output timing is specified at a nominal 50 pF load.
Figure 36. Timing Diagram—I2C Input/Output
1.3.15
J1850
See the MPC5200B User’s Manual (MPC5200BUM).
Table 41. I2C Output Timing Specifications—SCL and SDA
Sym
Description
Min
Max
Units
SpecID
1(1)
1 Programming IFDR with the maximum frequency (IFDR=0x20) results in the minimum output timings listed. The
I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed in IFDR.
Start condition hold time
6
—
IP-Bus Cycle(3)
A13.8
2(1)
Clock low time
10
—
IP-Bus Cycle(3)
A13.9
3(2)
2 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
SCL/SDA rise time
—
7.9
ns
A13.10
4(1)
Data hold time
7
—
IP-Bus Cycle(3) A13.11
5(1)
SCL/SDA fall time
—
7.9
ns
A13.12
6(1)
Clock high time
10
—
IP-Bus Cycle(3) A13.13
7(1)
Data setup time
2
—
IP-Bus Cycle(3) A13.14
8(1)
Start condition setup time (for repeated start condition
only)
20
—
IP-Bus Cycle(3) A13.15
9(1)
Stop condition setup time
10
—
IP-Bus Cycle(3)
3 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
A13.16
1
2
3
4
5
6
7
8
9
SCL
SDA
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