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參數(shù)資料
| 型號： | SPAKXC16Z1MFC16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.78 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, SMT-132 |
| 文件頁數(shù)： | 165/200頁 |
| 文件大?。?/td> | 1383K |
| 代理商： | SPAKXC16Z1MFC16 |
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MC68HC16Z1
MOTOROLA
MC68HC16Z1TS/D
67
3.6.4 Power-On Reset
When the SIM clock synthesizer is used to generate system clocks, power-on reset involves special cir-
cumstances related to application of system and clock synthesizer power. Regardless of clock source,
voltage must be applied to clock synthesizer power input pin VDDSYN, in order for the MCU to operate.
The following discussion assumes that VDDSYN is applied before and during reset — this minimizes crys-
tal start-up time. When VDDSYN is applied at power-on, start-up time is affected by specific crystal param-
eters and by oscillator circuit design. VDD ramp-up time also affects pin state during reset.
During power-on reset, an internal circuit in the SIM drives the IMB internal and external reset lines. The
circuit releases the internal reset line as VDD ramps up to the minimum specified value, and SIM pins
are initialized. When VDD reaches minimum value, the clock synthesizer VCO begins operation, and
clock frequency ramps up to limp mode frequency. The external RESET signal remains asserted until
the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running
and the internal reset signal is asserted for four clock cycles, these modules reset. VDD ramp time and
VCO frequency ramp time determine how long the four cycles take. Worst case is approximately 15 mil-
liseconds. During this period, module port pins may be in an indeterminate state. While input-only pins
can be put in a known state by means of external pull-up resistors, external logic on input/output or out-
put-only pins must condition the lines during this time. Active drivers require high-impedance buffers or
isolation resistors to prevent conflict.
3.6.4.1 Use of Three State Control Pin
Asserting the three-state control (TSC) input causes the MCU to put all output drivers in an inactive,
high-impedance state. The signal must remain asserted for 10 clock cycles in order for drivers to
change state. There are certain constraints on use of TSC during power-up reset:
When the internal clock synthesizer is used (MODCLK held high during reset), synthesizer ramp-
up time affects how long the 10 cycles take. Worst case is approximately 20 milliseconds from TSC
assertion.
When an external clock signal is applied (MODCLK held low during reset), pins go to high-imped-
ance state as soon after TSC assertion as 10 clock pulses have been applied to the EXTAL pin.
When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent mode
selection. Once the output drivers change state, the MCU must be powered down and restarted before
normal operation can resume.
3.7 Interrupts
Interrupt recognition and servicing involve complex interaction between the central processing unit, the
system integration module, and a device or module requesting interrupt service.
The CPU16 provides for eight levels of interrupt priority (0–7), seven automatic interrupt vectors, and
200 assignable interrupt vectors. All interrupts with priorities less than seven can be masked by the in-
terrupt priority (IP) field in the condition code register. The CPU16 handles interrupts as a type of asyn-
chronous exception.
Interrupt recognition is based on the states of interrupt request signals IRQ[7:1] and the IP mask value.
Each of the signals corresponds to an interrupt priority. IRQ1 has the lowest priority, and IRQ7 has the
highest priority.
The IP field consists of three bits (CCR[7:5]). Binary values %000 to %111 provide eight priority masks.
Masks prevent an interrupt request of a priority less than or equal to the mask value (except for IRQ7)
from being recognized and processed. When IP contains %000, no interrupt is masked. During excep-
tion processing, the IP field is set to the priority of the interrupt being serviced.
Interrupt request signals can be asserted by external devices or by microcontroller modules. Request
lines are connected internally by means of a wired NOR — simultaneous requests of differing priority
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