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參數(shù)資料
| 型號： | SP9604KS |
| 英文描述： | Quad, 12-Bit, Low Power Voltage Output D/A Converter |
| 中文描述： | 四，12位，低功耗，電壓輸出D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 185K |
| 代理商： | SP9604KS |
SP9604DS/03 SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
8
Figure 3. Latch Control Options — (a) Semi–Transparent Latch Mode; (b) Fully–Transparent Latch Mode
(a)
(b)
Figure 4. Timing
H
L
H
L
H
L
CLR
XFER
WR2
140ns, t
H
L
H
L
H
L
WR2
CS
WR1
140ns, t
Data Transfer from
Input Register to DAC's
Loads Input Data to
First Set of Latches
WR
XFER
on-reset. Using this feature, the
SP9604
can be
configured such that during power-up, the sec-
ond register will be digitally “zeroed”, produc-
ing a zero volt output at each of the four DAC
outputs. This is achieved by powering the unit
up with XFER in a high state. Thus, with no
external circuitry, the
SP9604
can be powered up
with the analog outputs at a known, zero volt
output level.
Temporarily forcing all DAC outputs to 0V
Set WR1=1, CS=1, WR2=0, XFER=0. The DAC
registers can be temporarily forced to 1000 0000
0000 by bringing the CLR pin low. This will force
the DAC outputs to 0V, while the CLR pin remains
low. When the CLR pin is brought back high, the
digital code at the DAC registers will again appear
at the DAC's digital inputs, and the analog outputs
will return to their previous values.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
OUT4
V
SS
V
DD
CLR
REF IN
GND
B1/B2
A
0
A
XFER
WR2
WR1
CS
V
OUT1
V
OUT3
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
DB
8
DB
9
DB
10
(MSB) DB
11
V
OUT2
SP9604
+5V –5V
12–Bit
V
OUT4
V
OUT3
V
OUT1
V
OUT2
Re+3V
GND
Address
DAC Strobe
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
OUT4
V
SS
V
DD
CLR
REF IN
GND
B1/B2
A
0
A
XFER
WR2
WR1
CS
V
OUT1
V
OUT3
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
DB
8
DB
9
DB
10
(MSB) DB
11
V
OUT2
SP9604
+5V –5V
12–Bit
V
OUT4
V
OUT3
V
OUT1
V
OUT2
Re+3V
GND
Address
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