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參數(shù)資料
| 型號： | SP9604KS |
| 英文描述： | Quad, 12-Bit, Low Power Voltage Output D/A Converter |
| 中文描述： | 四，12位，低功耗，電壓輸出D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 185K |
| 代理商： | SP9604KS |
SP9604DS/03 SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
3
0
DNLE, INLE Plots
CODE 4095
+0.25 lsb
DNLE
-0.25 lsb
+0.25 lsb
INLE
-0.25 lsb
SPECIFICATIONS
(continued)
(Typical @ 25C, T
MIN
≤
T
A
≤
T
MAX
; V
DD
= +5V, V
SS
= -5V, V
REF
= +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN.
TYP.
STABILITY
Gain
15
Bipolar Zero
15
SWITCHING CHARACTERISTICS
t
DS
Data Set Up Time
140
100
t
DN
Data Hold Time
0
t
WR
Write Pulse Width
140
100
t
XFER
Transfer Pulse Width
140
100
t
WC
Total Write Command
280
200
POWER REQUIREMENTS
V
–J, –K
3
V
–J, –K
3
Power Dissipation
30
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
-J, -K
0
Storage
-60
Package
-_P
28-pin Plastic DIP
-_S
28-pin SOIC
MAX.
UNITS
CONDITIONS
ppm/C
ppm/C
t
MIN
to t
MAX
t
MIN
to t
MAX
ns
ns
ns
ns
ns
to rising edge of WR1
Figure 4
Note 5
+5V, +3%; Note 4, 5
4
mA
-5V, +3%; Note 4, 5
4
mA
mW
+70
+150
°
C
°
C
Notes:
1.
Integral Linearity, for the
SP9604
, is measured as the arithmetic mean value of the magnitudes of
the greatest positive deviation and the greatest negative deviation from the theoretical value for any
given input condition.
Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
1 LSB = 2*V
REF
/4,096.
V
REF
= 0V.
2.
3.
4.
5.
The following power up sequence is recommended to avoid latch up: V
SS
(-5V), V
DD
(+5V), REF IN.
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