參數(shù)資料
型號: SP9504JP
元件分類: DAC
英文描述: QUAD, PARALLEL, WORD INPUT LOADING, 4 us SETTLING TIME, 12-BIT DAC, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁數(shù): 5/11頁
文件大?。?/td> 184K
代理商: SP9504JP
SP9504DS/03
SP9504 Quad, 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
3
DNLE, INLE plots
+0.25 lsb
DNLE
-0.25 lsb
+0.25 lsb
INLE
-0.25 lsb
0
CODE
4095
Vref = 3V
SPECIFICATIONS (CONTINUED)
(Typical at 25C; T
MIN ≤ TA≤TMAX; VDD = +5V, VSS = -5V, VREF = +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
SWITCHING CHARACTERISTICS
t
DS Data Set Up Time
140
100
ns
to rising edge of WR1
t
DN Data Hold Time
0
ns
Figure 4
t
WR Write Pulse Width
140
100
ns
t
XFER Transfer Pulse Width
140
100
ns
t
WC Total Write Command
280
200
ns
STABILITY
Gain
15
ppm/C
t
MIN to tMAX
Bipolar Zero
15
ppm/C
t
MIN to tMAX
POWER REQUIREMENTS
Note 5
V
DD
+5V, +3%; Note 4, 5
–J, –K
8
11
mA
V
SS
-5V, +3%; Note 4, 5
–J, –K
8
11
mA
Power Dissipation
80
mW
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
–J, –K
0
+70
°C
Storage
–60
+150
°C
Package
–_P
28–pin Plastic DIP
–_S
28–pin SOIC
Notes:
1.
Integral Linearity, for the SP9504, is measured as the arithmetic mean value of the magnitudes of
the greatest positive deviation and the greatest negative deviation from the theoretical value for any
given input condition.
2.
Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
3.
1 LSB = 2*V
REF/4,096.
4.
V
REF = 0V.
5.
The following power up sequence is recommended to avoid latch up: VSS (-5V), Vdd (+5V), REF IN.
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