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參數(shù)資料
| 型號(hào)： | SP9316B-4 |
| 英文描述： | 60 AMP LATCHING POWER RELAY |
| 中文描述： | 16？位CMOS乘法DAC |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 132K |
| 代理商： | SP9316B-4 |
Corporation
SIGNAL PROCESSING EXCELLENCE
185
Binary Input
111…111
100…001
100…000
011…111
000…001
000…000
Analog Output
-V
REF
(1-2
N
)
-V
REF
( +2
-N
)
-V
REF
( )
-V
REF
( -2
-N
)
-V
REF
(2
-N
)
0
Table 1. Unipolar Transfer Function
Individual latch controls are provided for the
high and low bytes which may be tied together
for a single 16-bit word update. The data is
latched with the strobe at logic 0. The latches are
level–triggered and can be made transparent by
tying them to logic 1. However, use of the
latches is recommended in most applications as
they significantly reduce data bit skew, which
affects the glitch performance.
Layout, Grounding and Guarding
16-bit system performance can be maintained
with suitable attention paid to the layout, ground-
ing and guarding techniques employed. All
grounds should be of as low resistance as pos-
sible. Analog and digital grounds should be
individually star-pointed and tied together as
close as possible to the
SP9316
. Good layout
techniques dictate that the high–speed digital
inputs should be kept separate from low–level
analog outputs. The DAC output and op amp
input are high impedance and so are sensitive to
interference from the digital input lines. Careful
pinout design of the
SP9316
has reduced this
problem to a minimum, but guarding of these
points should be considered. Figures 3 and 4
detail the low impedance guard track layout.
Amplifier Selection
The
SP9316
allows the designer to obtain the
optimum performance for each application. Se-
lection of the correct operational amplifier, and
the layout of the associated components are
critical to the success of the design. To obtain
the optimum linearity performance, the amplifi-
ers must have an open loop gain in excess of
100,000 or 100dB. Care should be taken to
ensure that the summing junction is as close to
analog ground as possible. Most applications
demand that the input offset be kept below
100
μ
V. To maintain accuracy over temperature,
the amplifiers should have low bias currents and
offset voltage temperature coefficients.
In bipolar applications, attention must be paid to
the choice of resistors R and 2R (see
figure 2
).
As the analog voltage output increases from
zero to full-scale, the power dissipated by the
feedback resistor increases and the resistor heats
up. This causes a small change in the resistance
value which could lead to an alteration to the
transfer function, which may be seen as integral
linearity errors. The internal resistor network
has been designed using ultra-stable thin-film
nichrome. It is important that the temperature
coefficient of the external resistors match those
in the DAC as closely as possible. Resistors
with a temperature coefficient of 10ppm/
°
C or
better should be used.
LONG TERM DRIFT
When measuring the stability of the
SP9316
,
great care should be taken to ensure that the drift
of the measurement instruments can be sepa-
Figure 2. Bipolar Operation
V
REF
BIT 1 (MSB)
MSB LATCH
LSB LATCH
_
+
SP9316
I
OUT1
400‰
DIGITAL
INPUT
+15V
I
OUT2
R
OS1
V
OUT
All "ones":
V
OUT
= –V
REF
+ 1LSB
0.01μF
1μF
+
17
18
13
14
R
FB
16
15
BIT 16 (LSB)
GND
NOTE:
To maintain specified linearity, the external amplifiers (A
and A
)
must be nulled. With a digital input of 10…0 and V
REF
set to zero —
1) set R
OS1
for V
O1
= 0V;
2) set R
OS2
for V
OUT
= 0V;
3) set V
REF
to +10V and adjust R
B
for V
OUT
= 0V
A
1
_
+
R
OS2
A
2
R
R for ±5V FS output
2R for ±10V FS output
2R
V
O1
Offset Binary Input
111…111
100…001
100…000
011…111
000…001
000…000
Analog Output
-V
REF
(1-2
-(N-1)
)
-V
REF
(2
-(N-1)
)
0
V
REF
(2
-(N-1)
)
V
REF
(1-2
-(N-1)
)
V
REF
Table 2. Bipolar Transfer Function
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