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參數(shù)資料
| 型號(hào)： | SP8720 |
| 廠商： | General Electric Company |
| 英文描述： | ECL two-modulus divider, with ECL10K compatible outputs |
| 中文描述： | ECL兩分頻器，與ECL10K兼容輸出 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 107K |
| 代理商： | SP8720 |
2
SP8720
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, the Electrical Characteristics are guaranteed over specified supply, frequency and temperature range
Supply voltage, V
CC
= 0V, V
=
2
5·2V
6
0·25V
Temperature, T
AMB
=
2
55
°
C to
1
125
°
C (A Grade),
2
30
°
C to
1
70
°
C (B Grade)
Value
Characteristic
Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
Output high voltage
Output low voltage
PE input high voltage
PE input low voltage
Clock to output delay
Set-up time
Release time
Symbol
f
MAX
f
MIN
I
EE
V
OH
V
OL
V
INH
V
INL
t
p
t
s
t
r
300
2
0·85
2
1·8
2
0·93
2·5
3
Min.
Max.
40
65
2
0·7
2
1·5
2
1·62
6
Units
Input = 400-800mV p-p
Input = 400-800mV p-p
V
EE
=
2
5·2V
V
EE
=
2
5·2V (25
°
C)
V
EE
=
2
5·2V (25
°
C)
V
EE
=
2
5·2V (25
°
C)
V
EE
=
2
5·2V (25
°
C)
Conditions
Notes
MHz
MHz
mA
V
V
V
V
ns
ns
ns
5
5
5
6
3, 6
4, 6
NOTES
1. The temperature coefficients of V
=
1
1·63mV/
°
C, V
=
1
0·94mV/
°
C and of V
IN
=
1
1·22mV/
°
C.
2. The test configuration for dynamic testing is shown in Fig.6.
3. The set-up time t
s
is defined as the minimum time that can elapse between L
→
H transition of control input and the next L
→
H clock pulse transition
to ensure that the
4
3 mode is obtained.
4. The release time t
r
is defined as the minimum time that can elapse between H
→
L transition of control input and the next L
→
H clock pulse transition
to ensure that the
4
4 mode is obtained.
5. SP8720B tested at 25
°
C only.
6. Guaranteed but not tested.
L
H
L
H
PE1
L
L
H
H
TRUTH TABLE FOR
CONTROL INPUTS
4
3
3
3
PE2
Division ratio
2000
1600
1200
800
400
0
0 100 200 300 400
INPUT FREQUENCY (MHz)
I
*
Tested as specified
in table of Electrical
Characteristics
GUARANTEED
*
OPERATING
WINDOW
T
AMB
=
2
55
°
C TO
1
125
°
C
Fig. 4 Typical input characteristic of SP8720A
Fig. 3 Timing diagram
2
t
r
t
s
1
CLOCK INPUT
PE INPUT
OUTPUT
2
2
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