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參數(shù)資料
| 型號(hào)： | SP8026 |
| 英文描述： | 200V/us Integrated APC Amplifier with Gain Adjust & Differential Output |
| 中文描述： | 200V/us綜合apc的放大器增益調(diào)整 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 93K |
| 代理商： | SP8026 |
3
Rev. 6/02/03
SP8024, 25, 26 200V/
μ
s Integrated APC Amplifier
Copyright 2003 Sipex Corporation
PIN DESCRIPTION
PIN NUMBER
NAME
FUNCTION
1
V
CC
Supply Voltage
2
GAIN
Gain Select
3
R
COM
Common connection point for R
GAIN
1 and R
GAIN
2
4
GND
Power Ground
5
R
GAIN1
Gain Adjust 1
6
R
GAIN2
Gain Adjust 2
7
V
OUT
-
Output Voltage -
8
V
OUT
+
Output Voltage +
Internal Operation
The SP8024/25/26 APC circuits have an inte-
grated photo detector and are designed with
three nominal sensitivities of 1mV/
μ
W, 2mV/
μ
W and 3mV/
μ
W respectively. Each part’s sen-
sitivity can also be adjusted continuously and
independently for two different gain modes via
two external resistors over a range of 12dB. The
two gain modes are controlled by a TTL com-
patible logic input. This logic input also normal-
izes the internal photo detector’s responsivity
for 650nm and 780nm laser wavelengths. The
logic pin selects between the two external gain
setting resistors to allow independent control
and settings for the two gain functions.
The 8024 APC family uses two stages of gain to
optimize for speed and offset. The two stages
consist of a differential trans-impedance ampli-
fier (TIA), and a differential gain adjust ampli-
fier.
TIA
The first stage is a differential trans-impedance
amplifier (TIA) for converting the photo detec-
tor output current to a balanced differential
voltage. This topology allows for fast settling of
the photo detector and also cancels offset ef-
fects. The TIA has no external components.
Variable Gain Amplifier
This stage is used to vary the gain of the system.
It provides selection for two different gain set-
ting resistors, R
GAIN1
and R
GAIN2
, at pins 5 and
6 via internal MOSFET switches S1 and S2. The
logic input at pin 2 controls the selection of the
two external gain set resistors.
Table 1: Gain Select Logic Truth Table
Gain
Select
Pin 2
Sensitivity
(mV/
μ
W)
R
G1
= R
G2
= 262
SP8024
SP8025
Rexternal,
Pin 3 to:
Gain
Factor (x)
SP8026
0 or Open
R
G1
- Pin 5
6.25
1
2
3
1
R
G2
- Pin 6
6.25
1
2
3
The gain of this balanced amplifier topology is
given by:
GAIN = 1 + Rf1 + Rf2
R
EXT
where R
GAIN
is external and Rf1 = Rf2 = 850
in feedback.
The nominal gain is defined as 6.25.
THEORY OF OPERATION
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