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參數(shù)資料
| 型號： | SNJ54LV166AFK |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-BIT PARALLEL-LOAD SHIFT REGISTERS |
| 中文描述： | 8位并行，負載移位寄存器 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 385K |
| 代理商： | SNJ54LV166AFK |
SCLS456B FEBRUARY 2001 REVISED DECEMBER 2004
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, V
CC
= 2.5 V
±
0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25
°
C
MIN
8
SN54LV166A
MIN
9
SN74LV166A
MIN
9
UNIT
MAX
MAX
MAX
tw
Pulse duration
CLR low
ns
CLK high or low
CLK INH before CLK
↑
Data before CLK
↑
SH/LD before CLK
↑
SER before CLK
↑
CLR
↑
inactive before CLK
↑
Data after CLK
↑
8.5
9
9
7
7
7
6.5
8.5
8.5
tsu
Setup time
7
8.5
8.5
ns
8.5
9.5
9.5
6
7
7
th
Hold time
0.5
0
0
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
±
0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25
°
C
MIN
6
SN54LV166A
MIN
7
SN74LV166A
MIN
7
UNIT
MAX
MAX
MAX
tw
Pulse duration
CLR low
ns
CLK high or low
CLK INH before CLK
↑
Data before CLK
↑
SH/LD before CLK
↑
SER before CLK
↑
CLR
↑
inactive before CLK
↑
Data after CLK
↑
6
7
7
5
5
5
5
6
6
tsu
Setup time
5
6
6
ns
5
6
6
4
4
4
th
Hold time
0
0
0
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
°
C
MIN
5
SN54LV166A
SN74LV166A
UNIT
MAX
MIN
MAX
MIN4
MAX
tw
Pulse duration
CLR low
5
5
ns
CLK high or low
CLK INH before CLK
↑
Data before CLK
↑
SH/LD before CLK
↑
SER before CLK
↑
CLR
↑
inactive before CLK
↑
Data after CLK
↑
4
4
4
3.5
3.5
3.5
4.5
4.5
4.5
tsu
Setup time
4
4
4
ns
4
4
4
3.5
3.5
3.5
th
Hold time
1
1
1
ns
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