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參數(shù)資料
| 型號： | SNJ54LV166AFK |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-BIT PARALLEL-LOAD SHIFT REGISTERS |
| 中文描述： | 8位并行，負(fù)載移位寄存器 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 385K |
| 代理商： | SNJ54LV166AFK |
SCLS456B FEBRUARY 2001 REVISED DECEMBER 2004
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The ’LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an
overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input.
When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each
clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs
on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the
low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a
clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low
enables the other clock input. This allows the system clock to be free running, and the register can be stopped
on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.
CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OUTPUTS
INTERNAL
CLR
SH/LD
CLK INH
CLK
SER
PARALLEL
A . . . H
QA
QB
QH
L
X
X
X
X
X
L
L
L
H
X
L
L
↑
↑
↑
↑
X
X
QA0
a
QB0
b
QH0
h
H
L
L
X
a . . . h
H
H
L
H
X
H
QAn
QAn
QB0
QGn
QGn
QH0
H
H
L
L
X
L
H
X
H
X
X
QA0
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