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參數(shù)資料
| 型號(hào)： | SNJ54LV165AW |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | PARALLEL-LOAD 8-BIT SHIFT REGISTERS |
| 中文描述： | 并行-載重8位轉(zhuǎn)換寄存器 |
| 文件頁(yè)數(shù)： | 6/17頁(yè) |
| 文件大?。?/td> | 472K |
| 代理商： | SNJ54LV165AW |
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SCLS402K APRIL 1998 REVISED APRIL 2005
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, V
CC
= 2.5 V
±
0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25
°
C
MIN
8.5
SN54LV165A
MIN
9
SN74LV165A
MIN
9
UNIT
MAX
MAX
MAX
tw
Pulse duration
CLK high or low
ns
SH/LD low
SH/LD high before CLK
↑
SER before CLK
↑
CLK INH before CLK
↑
Data before SH/LD
↑
SER data after CLK
↑
Parallel data after SH/LD
↑
SH/LD high after CLK
↑
11
13
13
7
8.5
8.5
tsu
Setup time
8.5
9.5
9.5
ns
7
7
7
11.5
12
12
1
0
0
th
Hold time
0
0
0.5
0.5
ns
0
0
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
±
0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25
°
C
MIN
6
SN54LV165A
MIN
7
SN74LV165A
MIN
7
UNIT
MAX
MAX
MAX
tw
Pulse duration
CLK high or low
ns
SH/LD low
SH/LD high before CLK
↑
SER before CLK
↑
CLK INH before CLK
↑
Data before SH/LD
↑
SER data after CLK
↑
Parallel data after SH/LD
↑
SH/LD high after CLK
↑
7.5
9
9
5
6
6
tsu
Setup time
5
6
6
ns
5
5
5
7.5
8.5
8.5
0
0
0
th
Hold time
0.5
0.5
0.5
ns
0
0
0
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
°
C
MIN
4
SN54LV165A
MIN
4
SN74LV165A
MIN
4
UNIT
MAX
MAX
MAX
tw
Pulse duration
CLK high or low
ns
SH/LD low
SH/LD high before CLK
↑
SER before CLK
↑
CLK INH before CLK
↑
Data before SH/LD
↑
SER data after CLK
↑
Parallel data after SH/LD
↑
SH/LD high after CLK
↑
5
6
6
4
4
4
tsu
Setup time
4
4
4
ns
3.5
3.5
3.5
5
5
5
0.5
0.5
0.5
th
Hold time
1
1
1
ns
0.5
0.5
0.5
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